Abstract: In an embodiment, an apparatus is disclosed that includes a memory slot including a certificate chain corresponding to an entity and a memory block. The memory block has protection enabled. The apparatus includes a processing device. The processing device is configured to receive a request message to clear protection for the memory block from a computing device of the entity. The request message includes a signature generated based at least in part on a private key of the entity. The processing device is configured to determine a public key corresponding to the entity based at least in part on the certificate chain, determine that the signature is valid based at least in part on the public key, determine that the protection for the memory block corresponds to the certificate chain and clear the protection for the memory block.

Abstract: In an embodiment, a semiconductor device is disclosed that includes at least one processing device and firmware including a dynamic demodulation engine. The dynamic demodulation engine, when executed by the at least one processing device, is configured to obtain a digital signal waveform, dynamically select a bit detection method based at least in part on a characteristic of the digital signal waveform, perform demodulation of the digital signal waveform using the selected bit detection method and generate decoded packets based at least in part on the demodulation.

Abstract: Systems and methods for demodulating a signal is described. A device can receive a modulated signal that encodes data. The device can sample a voltage of the modulated signal to generate a plurality of samples in digital domain. The device can determine in-phase data and quadrature data of the plurality of samples. The device can determine amplitude data and phase data based on the in-phase data and the quadrature data. The device can decode the amplitude data and phase data into digital symbols that represent the data encoded in the modulated signal.

Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Abstract: An apparatus includes a plurality of transceiver circuits, each comprising one or more phase shifter circuits. The phase shifter circuits may be configured to make a phase change by switching at least one of a capacitance value and an inductance value in response to a control signal. A characteristic impedance and the phase of each phase shifter circuit are correlated such that after the phase change, a value of the characteristic impedance is maintained at a predefined value.

Abstract: In an embodiment, an apparatus is disclosed that includes a first battery management circuit. The first battery management circuit is configured to measure a voltage of a first battery cell of a battery pack and to generate a first voltage measurement based at least in part on the measured voltage of the first battery cell. The first battery management circuit is configured to receive a bit of a first response from a second battery management circuit. The bit of the first response is generated by the second battery management circuit based at least in part on a measured voltage of a second battery cell of the battery pack. The first battery management circuit is configured to sum the bit of the first response with a corresponding bit of the first voltage measurement and to provide the summed bit to a third battery management circuit as part of a second response.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

Abstract: Systems and methods for calibrating a wireless power transmitter is described. A wireless power transmitter can include a controller and an amplifier module. The amplifier module can include an amplifier configured to amplify a voltage converted from a current proportional to power consumed by a wireless power transmitter, and a circuit connected to the amplifier. The circuit can be configured to receive a control signal from the controller. The circuit can be further configured to perform time division multiplexing on an output of the amplifier according to the control signal. A time division multiplexed output of the amplifier can include calibration data of the amplifier. The amplifier can be configured to output the time division multiplexed output to the controller.

Abstract: In an embodiment, a voltage reference circuit is disclosed that includes a first transistor circuit that is configured to receive an external supply voltage as an input and to output a first voltage and a chopper circuit that is configured to receive a second voltage as an input and to output a voltage reference. The chopper circuit has a breakage threshold. The voltage reference circuit further includes a second transistor circuit that is configured to receive the first voltage as an input and to output the second voltage at a value that is less than or equal to the breakage threshold of the chopper circuit.

Abstract: Apparatuses including multiple selectable circuit elements are described. In an example, an apparatus may include a power supply configured to output a voltage. The apparatus may further include a controller connected to the power supply and a transmission unit connected to the controller. The transmission unit may be configured to output power. The transmission unit may include comprising an inverter connected to the power supply. The inverter may include a high-side switching element. The transmission unit may further include a circuit element a circuit connected to the power supply. The circuit may be configured to select the circuit element. The circuit may include a switch connected between the inverter and the circuit element. The switch and the high-side switching element may be configured to be driven by the voltage outputted by power supply. The controller may be configured to control the power being outputted by the transmission unit.

Abstract: Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.

Abstract: Systems and methods for controlling data transaction between master and slave devices are described. A master device can be connected to multiple slave devices that can operate under one of a first, a second, and a third operation modes. The first operation mode can cause the master device to perform data transactions with the multiple slave devices via a network element and the multiple slave devices can be connected to one another via the network element. The second operation mode can disconnect the master device from the multiple slave devices, and multiple agents connected to the multiple slave devices can fulfill the data transactions. The third operation mode can cause the master device to perform data transactions with a first subset of the multiple slave devices via the network element, and can cause the master device to be disconnected from a second subset of the multiple slave devices.

Abstract: In an embodiment, a wireless power transmitter is disclosed that includes a first field-effect transistor, a second field-effect transistor a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first and second field-effect transistors. The analog front end includes a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor based at least in part on a pulse-width modulation signal and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor based at least in part on the pulse-width modulation signal.

Abstract: Methods, systems, and apparatuses for a single edge nibble transmission (SENT) multi-transmission mode are described. In an example, a system can include a transmitter and a receiver connected to one another. The transmitter may encode an identifier of a device in a synchronization nibble of a SENT signal. The transmitter may transmit the SENT signal with the encoded identifier to the receiver. The receiver may receive the SENT signal from the transmitter. The receiver may decode the identifier of the device from the synchronization nibble of the SENT signal to identify the device.

Abstract: Systems and methods for calibrating a wireless power transmitter is described. A wireless power transmitter can include a controller and an amplifier module. The amplifier module can include an amplifier configured to amplify a voltage converted from a current proportional to power consumed by a wireless power transmitter, and a circuit connected to the amplifier. The circuit can be configured to receive a control signal from the controller. The circuit can be further configured to perform time division multiplexing on an output of the amplifier according to the control signal. A time division multiplexed output of the amplifier can include calibration data of the amplifier. The amplifier can be configured to output the time division multiplexed output to the controller.

Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Abstract: In an embodiment, an apparatus is disclosed that comprises a plurality of resistors arranged as a reverse bridge and configured to convert an input voltage to a scaled output voltage. The scaled output voltage is scaled to a target format based at least in part on a range of the input voltage and a fixed value of the plurality of resistors. The input voltage is generated based at least in part on at least one signal generated by a sensor based at least in part on a measurement of a property of a measurement target. At least one of the plurality of resistors has a resistance value of R and at least another of the plurality of resistors has a resistance value of R plus or minus ?R.

Abstract: In an embodiment, a semiconductor device is disclosed that comprises a multiplexer. The multiplexer is configured to receive signals from each of a plurality of transmission coils of a wireless power transmitter as inputs and to output an output signal based at least in part on one of the signals. The semiconductor device further comprises an attenuator connected to the multiplexer that is configured to adjust a voltage of the output signal. The attenuator comprises a variable resistance. The semiconductor device further comprises a plurality of pull down circuits each corresponding to one of the transmission coils. The pull down circuits are configured to selectively clamp the signals received from the corresponding transmission coils to ground.

Abstract: Systems and methods for phase demodulation is described. A wireless power transmitter can include a controller, a transmission coil, and an integrated circuit connected to the controller and the transmission coil. The integrated circuit can be configured to measure a voltage of a transmission coil of a wireless power transmitter. The integrated circuit can be further configured to generate, based on the measured voltage, a pulse signal comprising a plurality of pulses. The integrated circuit can be further configured to send the pulse signal to the controller of the wireless power transmitter. The controller can be configured to perform phase demodulation using the pulse signal.