Abstract: The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.

Abstract: An over-temperature protection circuit is described. The circuit comprises an input for sensing a voltage across a transistor, a voltage-to-current converter configured to generate a current in dependence upon the voltage, an accumulator storing a value indicative of power dissipated by the transistor and which depends on the current; and a comparator configured to determine whether the value exceeds a threshold value and, in dependence on the value exceeding the threshold value, to generate a signal to cause the transistor to be switched off.

Abstract: A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.

Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.

Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

Abstract: Reliability and performance of a semiconductor device are improved. First, a first mask pattern is formed on the semiconductor substrate in each of first to third regions. Next, a second mask pattern made of a material that is different from a material configuring the first mask pattern is formed on a side surface of the first mask pattern and on the semiconductor substrate in each of the first to third regions. Next, by an anisotropic etching process performed to the semiconductor substrate, a plurality of fins protruding from the recessed upper surface of the semiconductor substrate are formed. In the manner, fins each having a different structure from that of a fin in the first region can be formed in the second and third regions.

Abstract: Example implementations include generating a guard service for a secure service at a secure region of a processing system by detecting a call to a secure service at a secure region of a processing device, obtaining a secure interface associated with the secure service, generating a guard interface based at least partially on the secure interface, generating a guard service based at least partially on the guard interface, locating the guard service at a secure region, and locating the guard interface at a secure address at the secure region.

Abstract: A semiconductor device includes: a first terminal connected to an antenna; a second terminal connected to an input terminal of a receiving circuitry; a third terminal connected to an output terminal of a transmitting circuitry; a first inductor arranged in a signal path extending from the first terminal to the second terminal; and a second inductor arranged in a signal path extending from the first terminal to the third terminal, and the first inductor and the second inductor are formed so as to have at least a partial overlapping portion in plan view.

Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

Abstract: A circuitry includes a first to fourth waveform synthesizers, each waveform synthesizer includes a first terminal and a second terminal to which input signals are input and a third terminal from which an output signal obtained by synthesizing the input signals is output. Frequencies of first to fourth input signals input to each waveform synthesizer are equal to each other, and phases of the second to fourth input signals are values delayed by approximately 180 degrees, delayed by approximately 90 degrees, and delayed by approximately 270 degrees, with respect to a phase of the first input signal. The output signal of each waveform synthesizer transitions from one state to the other state and transitions from the other state to the one state.

Abstract: The image processing device acquires feature quantities (maximum value, minimum value, average value, histogram, etc.) of the entire area (GA) of the image and feature quantities of each local area (LA) of the image from the input image, and calculates a plurality of modulation gain values (gamma correction curves) for GA and each LA. Furthermore, the image processing device determines the correction intensity for each LA from the feature quantity of the GA and the feature quantity of each LA, and creates the LA correction intensity map. Finally, the image processing device finally applies the result of combining a plurality of modulation gain values based on the LA correction intensity map to the input image.

Abstract: A calculation accuracy of a communication quality for use in selecting a communication path is improved. A radio communication device includes: a first calculator configured to calculate a transmission quality indicator value of each of a plurality of parent candidate nodes on the basis of a transmission frame transmitted from an own device to each of the plurality of parent candidate nodes; a second calculator configured to calculate a reception quality indicator value of each of the parent candidate nodes on the basis of a reception frame transmitted from each of the plurality of parent candidate nodes and received by the own device; and a selector configured to select a parent node for use in the communication path among the plurality of parent candidate nodes on the basis of the transmission quality indicator value and the reception quality indicator value.

Abstract: A voltage divider circuit includes: a first voltage divider having first and second capacitors, and an output node configured to output a divider voltage from between the first and second capacitors; a second voltage divider having third and fourth capacitors, and first to third switches, and being connected in parallel to the first voltage divider; and a fourth switch provided between the output node and a connection node of the third and fourth capacitors. In the voltage divider circuit, the switches are controlled based on controlling periods.

Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Abstract: Provided is a technique capable of improving test efficiency of semiconductor devices. A test apparatus includes a probe card having a plurality of measurement sites that contact with a plurality of semiconductor devices formed on a semiconductor wafer; a control unit configured to generate map information, probe-card form information, and contact-position information, the map information including position information and peculiar information of the semiconductor devices on the semiconductor wafer, the probe-card form information including arrangement information of the measurement sites, the contact-position information indicating a contact position that is a range of the semiconductor device tested at one time by the probe card based on constrained-condition information of limiting contact with the probe card; and a position control unit configured to control a relative position between the probe card and the semiconductor wafer based on the contact-position information.

Abstract: The semiconductor device includes: a current detection circuit configured to detect a current flowing through a three-phase motor by driving of a drive circuit; and a controller configured to control the drive circuit, based on the detected current. The controller is configured to control, when the three-phase motor is stationary, an energization pattern in such a way that a wave detection current sequentially flows from the drive circuit to each phase of the three-phase motor, to obtain, from the wave detection current detected by the current detection circuit, a first, a second and a third interphase current differences, each of which is a difference among wave detection currents flowing in directions opposite to one another, to determine the energization pattern based on a magnitude relationship among the first, the second and the third interphase current differences.

Abstract: A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.