Patents Assigned to Renesas Eletronics Corporation
  • Patent number: 9281329
    Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 8, 2016
    Assignee: RENESAS ELETRONICS CORPORATION
    Inventors: Akie Yutani, Yasutaka Nishioka
  • Publication number: 20130270648
    Abstract: Replacement metal gates well suited for self-aligned contact formation are made by replacing the dummy gate with a recessed polysilicon layer and then effecting an aluminum-polysilicon substitution. The resulting upper polysilicon layer is easily removed from the recessed aluminum layer, which can then be protected with a protective dielectric layer for subsequent formation of a source or drain contact hole.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 17, 2013
    Applicant: Renesas Eletronics Corporation
    Inventor: Kenzo MANABE
  • Patent number: 8292159
    Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: October 23, 2012
    Assignees: Renesas Eletronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Hiroshi Maki, Yukio Tani