Patents Assigned to Renesas Semiconductor Package & Test Solutions Co., Ltd.
  • Patent number: 10490486
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 26, 2019
    Assignees: Renesas Electronics Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 10115658
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 30, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 9793342
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 17, 2017
    Assignees: Renesas Electronics Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 9733273
    Abstract: The time required to test an electronic device mounted in semiconductor manufacturing equipment can be reduced. A first test panel mounted, on a first connector surface thereof, with plural first test-object connectors respectively including plural first terminals electrically coupled to an electronic device and a second test panel mounted, on a second connector surface thereof, with plural second test-object connectors respectively including plural spring probes are provided. The first connector surface of the first test panel and the second connector surface of the second test panel are positioned to face each other, the spring probes included in the second test-object connectors are electrically coupled to the first terminals included in the first test-object connectors, and a functional test concerning an electrical characteristic of the electronic device is performed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
    Inventor: Yusuke Nakajima
  • Patent number: 9496204
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 15, 2016
    Assignees: RENESAS ELECTRONICS CORPORATION, RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 9484288
    Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: November 1, 2016
    Assignees: Renesas Technology Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd.
    Inventor: Yoshihiko Shimanuki