Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: A current-mode D/A converter is described having variable output and offset control. According to an exemplary embodiment, a first D/A converter includes a number of first control inputs and an output capable of generating a first current proportional to a number of active first control inputs. A driver includes an input connected to the output of the first D/A converter, a number of second control inputs, and an output capable of generating a second current proportional to the first current based on a number of active second control inputs. A second D/A converter includes a number of third control inputs and an output capable of generating a third current proportional to a number of active third control inputs. Offset control circuitry includes an input connected to the output of the second D/A converter, an offset control input, and an output connected to the output of the driver.

Abstract: Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a changeable set of a plurality of input terminals, a second request is associated with a changeable one of the input terminals, and a third request is associated with a fixed one of the input terminals. One of the first, second, and third requests is received, and an analog signal presented at one of the input terminals is converted into a digital value based on the received one of the first, second, and third requests. When one of the second and third requests is received while converting a plurality of analog signals presented at the changeable set of the input terminals, a determination can be made whether the changeable set of the input terminals includes the one of the changeable and fixed input terminals associated with the received request.

Abstract: Methods and apparatus to detect terminal open circuits and short circuits to ground in inductive head write drivers are presented. A exemplary method is provided for detecting a short-circuit condition at at least one of a pair of write head terminals of a write driver, the write driver producing a write current that, when passed through a inductive head assembly coupled to the pair of write head terminals, polarizes the inductive head according to a direction of the write current. The method includes the step of generating a first current that is proportional to at least a portion of the write current that flows in a first direction into a first write head terminal of the write driver. A second current is generated that is proportional to at least a portion of the write current that flows in a second direction, opposite the first direction, into a second write head terminal of the write driver.

Abstract: Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a plurality of input terminals and a second request is associated with one of the input terminals. An analog signal presented at each of a portion of the input terminals associated with the first request is converted in succession into a digital value until the one of the input terminals associated with the second request is reached. A predetermined amount of time is waited to receive the second request. An analog signal presented at each of a remaining portion of the input terminals associated with the first request is converted in succession into a digital value when one of an expiration of the predetermined amount of time and a receiving of the second request occurs.

Abstract: Method and apparatus for programming non-volatile, programmable, electrically-erasable memory using a USB interface are presented. According to one aspect, a method for in-system programming of non-volatile, programmable, electrically erasable device memory using a USB interface includes the steps of: enumerating at least one device onto a USB bus with a first hardware configuration; encapsulating programming commands and program data into USB packets according to a custom protocol; sending the USB packets including the encapsulated programming commands and program data to the at least one device over the USB bus; and programming at least a portion of the device memory in response to receiving the programming commands and program data at the at least one device. At least partial functionality of the at least one device as defined by the first hardware configuration is maintained while the device memory is programmed.

Abstract: A circuit is tested for latch-up by scanning an optical beam across the surface, supplying power to the integrated circuit, monitoring the power of the power supply, and detecting latch-up in the integrated circuit by capturing an image of the integrated circuit when the power reaches a predetermined threshold. The captured image is compared with a baseline image to determine where latch-up occurs in the circuit.