Patents Assigned to Resilience Corporation
  • Publication number: 20100205604
    Abstract: A system and method for managing multiple instances of a software application running on a single operating system is described. The system may be a server which hosts multiple copies of the same software application running in real time within a framework. The framework prevents the multiple copies of the application from interfering with one another.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: Resilience Corporation
    Inventors: Eric T. Brower, Jonathan Lundell, Eric L. Green
  • Patent number: 6349391
    Abstract: A redundant clock system for use in a computer is provided including a first oscillator which produces first reference clock signals; a second oscillator which produces second reference clock signals; a third oscillator which produces third reference clock signals; a first multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a second multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a third multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a first phase-locke
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: February 19, 2002
    Assignee: Resilience Corporation
    Inventors: James L. Petivan, Jonathan K. Lundell, Don C. Lundell
  • Patent number: 6240526
    Abstract: A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module inc
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: May 29, 2001
    Assignee: Resilience Corporation
    Inventors: James L. Petivan, Jonathan K. Lundell, Don C. Lundell
  • Patent number: 6141769
    Abstract: A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module inc
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: October 31, 2000
    Assignee: Resilience Corporation
    Inventors: James L. Petivan, Jonathan K. Lundell, Don C. Lundell