Abstract: A circuit for recycling energy in bit lines (BL and BLB) of SRAM during write operation by (i) storing the charges BL and BLB to an intermediate voltage source (VLB) in a discharge phase and (ii) restoring the charges from the intermediate voltage, back to the BL or BLB in a recovery phase. The circuit includes an inductor, a pair of NMOS transistors, a series resonance node, and an energy source (VLB) in addition to the components of an SRAM input-output circuit shown as in FIG. 1. During the SRAM write operation, the BL or BLB is discharged to the energy source VLB through the pair of NMOS transistors and, the inductor and the series resonance node. The remaining energy in the BL and the BLB is discharged to ground using the write complementary write drivers.

Abstract: Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.

Abstract: Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).