Abstract: Static and dynamic power is saved in systems on a chip (SoCs) with an array of multiple RISC cores by adjusting power consumption using a combination of architecture and algorithm. Elements can be turned on and off with a higher granularity as compared to conventional implementations. An event distributor/power manager matches input queues queue occupancy to how many elements need to be active continuously to process incoming events without delaying event processing. Both instantaneous and average power can be controlled, in particular reduced to lower levels than in conventional systems while maintaining continuous processing of a varying level (number) of received events. Resulting power consumption is optimally tuned to the instantaneous workload. As compared to conventional solutions, the current implementation is a complex system approach taking into considerations multiple factors, and the algorithm can be implemented autonomously for more dynamic system re-configuration (than conventional solutions).

Abstract: A system and method for bypassing server CPU by redirecting data transactions between network and disk provides an innovative implementation for intercepting network to disk data traffic and performing transactions on this data using internal logic rather than a CPU, providing transparent functionality with improved performance as compared to conventional solutions. This is particularly useful in sending and receiving data blocks between network connections and disk storage, such as in distributed storage servers.

Abstract: An apparatus and method of bypassing server DRAM by redirecting internal data transactions to an embedded buffer provides an innovative implementation for intermediate storage for internal transactions, providing transparent functionality with improved performance as compared to conventional solutions. Transaction throughput is improved at least in part by avoiding using conventional DRAM, thus eliminating conventional bottlenecks in DRAM intermediate storage. The current embodiment is particularly useful in sending and receiving data blocks between disk storage and network connections.

Abstract: A storage virtualization offload engine (SVOE) optimizes network storage stack applications, providing an innovative implementation for network storage event processing. The current embodiment is particularly suited for distributed storage servers, offloading storage related functions from CPU to a co-processor. The SVOE improves system performance and power consumption by executing heavy operations (such as wide vector computations) by dedicated hardware engines. Thus, the SVOE avoids the significant overhead and overall task latency of a CPU using system calls in the middle of software thread to offload processing. A system includes two or more event processing elements (EPEs). Each EPE is configured for receiving events that include respective tasks and for processing only data access portions of the tasks.

Abstract: A Software Enabled Network Storage Accelerator (SENSA) system includes a number of SENSA components. The components can be implemented individually or in combination for a variety of applications, in particular, data base acceleration, disk caching, and event stream processing applications. Hardware (HW) real time operating system (RTOS) optimization for network storage stack applications such as event processing avoids conventional CPU usage by processing the payload, or internal data, of a packet using an array of at least two event processing elements (EPEs), each EPE in the array configured for: receiving events, each of the events having a task corresponding to the event; and processing the task in run-to-completion manner by operating on some portions of the task and offloading other portions of the task.

Abstract: A server receives requests as events from a client via a network. Each event includes a respective task that requires access to disk storage. The server includes one or more processors that process the tasks in a run-to-completion manner and two or more hardware engines to which the processor(s) offload(s) at least some of the processing of the tasks. The hardware engines perform computation-intensive operations such as table lookups and hashes. Preferably, if there are more than one processor, the processors are identical RISC-core event processing elements, all configured with identical instruction code for execution. Preferably, the server also includes a network interface card; the processor(s) and the hardware engines may be part of either the network interface card or a separate co-processor.