Abstract: A RAM module that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the RAM module to perform its access and pre-charge during the dips and posts of the optimized clock signal, the RAM module can perform multiple accesses and pre-charges during one clock cycle. The RAM module can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal optimizer may be constructed. The critical time is the longest interval of time required for a worst-case scenario memory access. A signal optimizer transforms the clock signal into a signal that has a higher frequency than the original clock signal and maintains both its high state and its low state for at least the critical time. By then allowing the synchronous SRAM chip to perform its access and pre-charge during the dips and posts of the optimized clock signal, the synchronous SRAM chip can perform multiple accesses and pre-charges during one clock cycle. The SRAM chip can be used for direct memory accesses such that the processor does not need to arbitrate access to the memory.

Abstract: RAM cells having a substantially balanced number of N-MOS and P-MOS transistors are disclosed. In a two-port RAM cell the invention uses an N read-write port comprising N-MOS transistors and a P read-port comprising P-MOS transistors. In a three-port RAM cell having one read-write port, the invention adds another N read-port comprising N-MOS transistors to the same two-port RAM cell. In effect, for each read-port added to a RAM cell, the invention alternates between a P read-port and then an N read-port. In a RAM cell having multiple N read-write-ports and multiple read-ports, the invention selects the number of P read-ports and/or the number of N read-ports such that the number of N-MOS transistors in the RAM cell are substantially the same as the number of P-MOS transistors. The invention is thus advantageous over the prior art because the invention provides a more balanced number of N-MOS and P-MOS transistors in each RAM cell, which better utilizes the layout areas.