Patents Assigned to S.O.I.Tech Silicon On Insulator Technologies
  • Patent number: 6884697
    Abstract: The invention relates to improvements in a process and annealing device for cleaving a wafer layer along a weakened zone in a donor wafer using a thermal anneal. In one improvement, at least one donor wafer is provided in a substantially horizontal position during the thermal anneal to prepare a wafer layer which, after detachment, has a cleaved surface with reduced surface roughness irregularities. The donor wafer can be preferably placed inside a chamber between two heating electrodes during the thermal anneal. The thermal anneal can be conducted to detach the wafer layer or the donor wafer to mechanical action to detach the wafer layer after the thermal anneal is conducted. Either way, a cleaved surface is provided on the detached wafer layer that does not include isolated dense areas adjacent the wafer layer periphery.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: April 26, 2005
    Assignee: S.O.I.Tech Silicon on Insulator Technologies S.A.
    Inventors: Walter Schwarzenbach, Christophe Maleville
  • Patent number: 6576065
    Abstract: The invention relates to an installation for treating wafers made of materials serving as microelectronics substrates including a tank for containing a treatment bath, a wafer support device capable of receiving at least one wafer of a first size, and an element for grasping and placing each wafer of the first size in the bath and for removing it therefrom. The installation further includes a support for receiving at least one wafer of a second size that is smaller than the first size, the shape of the support allowing it to be grasped by the grasping element and received by the wafer support device in the tank.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 10, 2003
    Assignee: S.O.I.Tech Silicon On Insulator Technologies
    Inventor: Jean-Michel Lamure