Abstract: A genetically engineered yeast cell with enhanced activity of an EDC protein compared to that of a parent cell and capability of producing lactate, a method of producing the yeast cell, and a method of producing lactate by using the yeast cell.

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract: In a lower substrate, a display apparatus having the lower substrate and a method of manufacturing the lower substrate, the lower substrate includes a pixel area and a circuit area. An image is displayed in the pixel area. A first signal electrode is disposed in a circuit area. A first insulating layer includes an opening, through which the first signal electrode is exposed. A second signal electrode is disposed on the first insulating layer in the circuit area, and spaced apart from the first signal electrode. A second insulating layer is disposed on the first insulating layer, and includes a contact hole, through which the first and second signal electrodes are exposed. A conductive layer electrically connects the first signal electrode to the second signal electrode. Therefore, a manufacturing process is simplified so that a yield of the lower substrate is increased.

Abstract: There is provided a convergence adjusting apparatus and method using spline interpolation in a projection image display device. In the convergence adjusting apparatus, a controller calculates the unknown coefficients of a cubic spline interpolation polynomial for each line segment separated by adjustment points on a horizontal or vertical line to interpolate between the adjustment points, a memory temporarily stores the unknown coefficients, a coordinate position generator counts horizontal sync signal pulses and calculates the square and cube of the count value, a plurality of multipliers multiply the count value, the square, and the cube by the unknown coefficients received from the memory, respectively, and an adder adds convergence adjustment point data received from the memory and the outputs of the multipliers and outputs interpolation values.

Abstract: A method for fabricating complementary metal-oxide-semiconductor (CMOS) devices and circuits resulting therefrom are provided. The method includes forming the source and drain regions of the CMOS device by out-diffusion of ions injected into a conductive spacer. The method also includes forming the gate electrode after the source and drain regions have been activated by heat treatment. By forming the gate electrode after heat treating the source and drain regions, the material used to form the gate electrode is not distorted due to heat.

Abstract: A method of forming a capacitor of semiconductor devices, and the capacitor formed thereby, improves the reliability of semiconductor devices by maximizing the capacitance of the capacitor through the stable increase of the surface area of its lower electrode material layer.

Abstract: A semiconductor memory device is tested by sequentially coupling a plurality of global input/output lines to a comparator which compares data bits from the global input/output lines sequentially rather than in parallel so as to reduce the number of output sense amplifiers. This reduces both the chip area, and the excessive current consumption caused by large numbers of sense amplifiers operating in parallel. The memory device includes a plurality of global input/output lines coupled to a memory cell array to receive data from the memory cell array. A global line select circuit generates sequential global line select signals during a test operation. A plurality of switch circuits selectively couples data from the global input/output lines to a sense amplifier responsive to the global line select signals. A comparator coupled to the output port of the sense amplifier sequentially compares a sequence of test data output from the sense amplifier and generates a result signal during the test operation.

Abstract: There is provided a mute control circuit which is simplified to efficiently remove switching noise during the muting of each output and reducing the number of connection pins required for a given integrated circuit. The mute control circuit includes a pulse generator for receiving the each mute signal and generating a control pulse; a charge/discharge signal generator for receiving the control pulse and generating a charge/discharge signal and a switching control signal; a controller for receiving the charge/discharge signal and controlling the mute operation of the output terminal according to the switching control signal; and a switching signal generator for receiving the mute signal, generating a switching signal according to the switching control signal of the charge/discharge signal generator, and supplying the switching signal to the controller.

Abstract: A method and apparatus for implementing a prefetch scheme in which a plurality of data are simultaneously read from memory cells of sequential addresses synchronized to an external signal and serially transferred from the memory cells to a temporary latch circuit which has a number of bits corresponding to the member of bits in the prefetch scheme. The bits in the temporary latch circuit are multiplexed and sequentially driven out of the memory device. The memory device includes a plurality of memory cells which are connected to an input/output line pair through a plurality of column select gates, each of which is controlled by an independent chip select line. A sense amplifier is connected to the input/output line pair for sensing and amplifying data from the input/output lines and to transmit data to the input/output lines. A data output buffer transfers the data from the sense amplifier to the outside of chip.