Abstract: Embodiments of the invention may provide systems and methods for detecting the presence a DTV signal such as an ATSC DTV signal. The system and methods may be applied to a received RF signal that has been down-converted to a baseband or low-IF digitized signal. The systems and methods may detect a presence of a DTV signal by searching for its characteristic pilot signal, known to reside in a fixed frequency range for all valid DTV signals. This pilot signal may be extracted by processing the baseband or low-IF signal in multiple stages. The first stage may reduce the signal information to that pertaining to the frequency band covering all valid pilot frequencies and commensurately reduces the sampling rate, and hence computational complexity of subsequent operations. A second stage may then efficiently operate on this reduced rate signal to focus on a series of particular pilot frequencies for interrogation.

Abstract: Embodiments of the invention may provide for reducing interference in the front-end of a communications receiver. The cancellation circuitry may be utilized in conjunction with a preliminary rejection filter for improved rejection of out-of-band interference from other radio services or circuitry. The cancellation circuit may be placed in parallel with the preliminary rejection filter and may enhance suppression at the interference frequency by matching the gain and phase of the preliminary rejection filter prior to subtracting the matched signal from the preliminary rejection filter output. The cancellation circuit need not necessary know beforehand the characteristics of the preliminary rejection filter, the interference source, or the coupling mechanism, as it may adapt to unknown or varying interferers by adapting the matching gain and phase values based on the output of the preliminary rejection filter at tap points occurring both before and after application of the cancellation signal.

Abstract: Embodiments of the invention may provide for reducing interference in the front-end of a communications receiver. The cancellation circuitry may be utilized in conjunction with a preliminary rejection filter for improved rejection of out-of-band interference from other radio services or circuitry. The cancellation circuit may be placed in parallel with the preliminary rejection filter and may enhance suppression at the interference frequency by matching the gain and phase of the preliminary rejection filter prior to subtracting the matched signal from the preliminary rejection filter output. The cancellation circuit need not necessary know beforehand the characteristics of the preliminary rejection filter, the interference source, or the coupling mechanism, as it may adapt to unknown or varying interferers by adapting the matching gain and phase values based on the output of the preliminary rejection filter at tap points occurring both before and after application of the cancellation signal.

Abstract: Systems and methods are provided for positive and negative feedback of cascode transistors for a power amplifier. The systems and methods may include a first cascode stage comprising a first common-source device and a first common-gate device; a second cascode stage comprising a second common-source device and a second common-gate device; a first degenerative element or block provided for the first common-source device; a second degenerative element or block provided for the second common-source device; a first positive feedback block or element that connects a first gate of the first common-source device with a second drain of the second common-source device; and a second positive feedback block or element that connects a second gate of the second common-source device with a first drain of the first common-source device.

Abstract: An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier.

Abstract: A tunable capacitor device may be provided in accordance with example embodiments of the invention. The tunable capacitor device may include a first capacitor; a second capacitor; a third capacitor, where the first, second, and third capacitors are connected in series, wherein the second capacitor is positioned between the first capacitor and the second capacitor; and at least one switch transistor, where the at least one switch transistor is connected in parallel with the second capacitor.

Abstract: Systems and methods are provided for power amplifiers with discrete power control. The systems and methods may include a plurality of unit power amplifiers; a plurality of primary windings, wherein each primary winding is connected to at least one respective output port of a respective one the plurality of unit power amplifiers; a secondary winding inductively coupled to the plurality of primary windings, where the secondary winding provides an overall output; a bias controller, where the bias controller provides a respective bias voltage based at least in part on a level of output power to one or more of the plurality of unit power amplifiers; and a switch controller, where the switch controller operates to activate or deactivate at least one of the plurality of unit power amplifiers via a respective control signal.

Abstract: A system for a power transmitter may be provided. The system may include a first amplifier stage having at least a first transistor and a second transistor that are connected in a first cascode configuration; a second amplifier stage having at least a third transistor and a fourth transistor that are connected in a second cascode configuration, where the first transistor receives a system input of the power transmitter, where the second transistor is connected to the third transistor, and where the fourth transistor provides a system output of the power transmitter; and a feedback network that connects a first gate or base of the fourth transistor with a second gate or base of the second transistor.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: A power amplifier system in accordance with an example embodiment can utilize a transformer having a primary winding inductively coupled to a secondary winding, where the primary winding includes a center tap between a first port and a second port, where the secondary winding includes a third port and a fourth port, where the primary winding receives a first output from a first amplifier, where the center tap receives a second output from a second amplifier.

Abstract: A multi-primary and distributed transformer is provided for one or more sets of parallel-connected or series-connected power amplifiers. The transformer may include a plurality of primary windings, including a first primary winding, a second primary winding, a third primary winding, and a fourth primary winding, where each of the plurality of primary windings is not directly connected to any other of the plurality of primary windings, where each primary winding includes a respective positive port and a negative port for receiving respective differential signals, where each primary winding include a respective first number of turns; and a single secondary winding having a plurality of segments, including a first segment and a second segment, where each segment includes a second number of turns, the second number of turns greater than or equal to the respective first number of turns, where the single secondary winding includes at least one output port.

Abstract: A SPDT or SPMT switch may include a transformer having a primary winding and a secondary winding, where a first end of the secondary winding is connected to a single pole port, where a first end of the primary winding is connected to a first throw port; a first switch having a first end and a second end, where the first end is connected to ground; and a second switch, where a second end of the secondary winding is connected to both a second end of the first switch and a first end of the second switch, where a second end of the second switch is connected to a second throw port, where the first switch controls a first communication path between the single pole port and the first throw port, and where the second switch controls a second communication path between the second throw port and the single pole port.

Abstract: System and methods are provided for multi-path orthogonal recursive predistortion. The systems and methods may include generating a first orthogonal signal and a second orthogonal signal, where the first and second signals are orthogonal components of an input signal and processing, at a first predistortion module, the first orthogonal signal and a first error correction signal to generate a first predistorted signal.

Abstract: Systems and methods are disclosed for providing a linear polar transmitter. The systems and methods may include generating an input amplitude signal and an input phase signal, where the input amplitude signal and the input phase signal are orthogonal components of an input signal, and where the input amplitude signal and the input phase signal are generated on respective first and second signal paths. The systems and methods may also include processing the input amplitude signal along the first signal path using an amplitude error signal to generate a predistorted amplitude signal, and processing the input phase signal along the second signal path using an phase error signal to generate a predistorted phase signal.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a ?60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Abstract: Embodiments of the invention may provide for enhancement systems and methods for a power amplifier output control system. In an example embodiment, driver amplifier control may be provided in conjunction with power amplifier control to improve the power efficiency and/or dynamic range of the transmitter system. Furthermore, control over the driver amplifier may allow for relaxed power control slope, which may lessens the burden of digital to analog converters (DACs) in transmitter systems such as cellular transmitter systems. Also, systems and methods in accordance with example embodiments of the invention may provide a less sensitive solution to operational environment variations such as temperature, battery power voltage and implementation IC process.

Abstract: Embodiments of the invention may provide for systems and methods for providing a power amplifier with integrated passive device, thereby improving the performance of the power amplifier. The power amplifier may include a signal amplification section, a power combining section, and a coupling device section that interconnects the signal amplification section and the power combining section. The signal amplification section may be implemented on a first substrate, and the power combining section may be implemented on a second substrate, where the first substrate and the second substrate may be different. The power combining section may be implemented by the integrated passive device (IPD) that may have characteristics of high performance passive device with flexibility of implementing diverse functions, including a notch filter, a low pass filter, and/or bypass capacitance for bias network. The power combining section implemented by the integrated passive device may have an improved power combining efficiency.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.