Abstract: In a particular embodiment, at a controller coupled to a memory array, a method includes receiving an indication that a first group of data bits read from the memory array includes errors that are uncorrectable by an error correction coding (ECC) engine. A count of the first group of data bits having a particular bit value may be compared to a prior count of data bits having the particular bit value. In response to determining that the count exceeds the prior count, a bit of the first group of data bits that has the particular bit value and that corresponds to a same memory cell as a corrected data bit of a second group of data bits is identified. A value of the identified bit of the first group may be changed to generate an adjusted group of data bits. The adjusted group of data bits may be provided to the ECC engine.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.

Abstract: In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

Abstract: Various embodiments include an apparatus and a method to secure protected digital document content from tampering by their user, such as unauthenticated use or use violating a policy of the digital document. The digital document file can be transferred from a network node such as a web site server to a digital appliance, such as a computer, in encrypted form. The digital document file can be resident already on a device, and/or be transferred into a device that is connected to the digital appliance. The device (hereafter a DRM device) can internally store the digital document or part of the document. The DRM device may decrypt the digital document when requested to do so. The device may further format the content for usage, for example, convert text into its graphic bitmap representation. Device formatting can include sending plain text data to the digital appliance. The device may further process degradation to the resulted file, for example, reduce the resolution of the graphic representation.

Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

Abstract: A substrate of a non-volatile storage system includes selected regions in which additional ions are deeply implanted during the fabrication process. NAND strings are formed over the selected regions such that end word lines of the NAND strings are over the deeply implanted ions. The presence of the deeply implanted ions below the end word lines increases a channel capacitance of the substrate under the end word lines. Due to the increased capacitance, boosting of a channel in the substrate below the end word lines is reduced, thereby reducing the occurrence of gate induced drain leakage (GIDL) and band-to-band tunneling (BTBT) and, consequently, program disturb. A shallow ion implantation may also be made to set a threshold voltage of storage elements of the NAND string.

Abstract: Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines.

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract: A charge pump system using a current based regulation method, in addition to the typical voltage based regulation methods is presented. The current flow in the charge pump is determined independently of the output voltage. By sensing the current going through the charge pump while its output is being regulated to the target level, the strength of charge pump can be dynamically adjusted in term of regulation level, branch assignment, clock frequency, clock amplitude, and so on. Indirectly sensing the current going through pump (not in serial with output stage to allow additional IR drop) will allow the pumps to have matrix of V and I to better adjust the charge pump parameters for current saving and ripple reduction.

Abstract: Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

Abstract: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

Abstract: A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series and a corresponding set of multiple gate stages connected in series, where the output stages have the same structure as the corresponding gate stages. The switches that the provide the output of each output generation stage are controlled by the corresponding gate stage. The number of output stages that are active in boosting the voltage self-adapts according to the output level being regulated, with the later stages changing from a boosting operation to a filtering function with not being used to active boost the output.

Abstract: In order to maintain a memory system's performance levels to its end-of-life, latency threshold level(s) are specified and associated with different memory system operating parameters. In one embodiment, the memory system monitors and gathers performance statistics in real time, and in accordance with specific memory transfer sizes. A current latency level can be dynamically calculated using the performance statistics and compared to previously established latency threshold levels. If the current latency level is greater than or equal to a specific latency threshold level, the memory system's configuration setting can be adjusted according to the operating parameters associated with the latency threshold level to offset the increased latency.

Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.

Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.

Abstract: A non-volatile storage system can selectively perform one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line) without intentionally erasing other non-volatile storage elements that are connected to the common word line (or other type of control line) but not in the subset.

Abstract: A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N?1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N?1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N?1, N, and N+1.