Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.