Abstract: A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.

Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, and memory stack structures vertically extending through a respective one of the alternating stacks and located within the first memory array region and the second memory array region. An inter-array region containing lower and upper staircases is located between the first and the second memory array regions. The first memory array region may have a greater length than the second memory array region, or the lower staircase may generally ascend in an opposite direction from the upper staircase.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

Abstract: Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

Abstract: A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Abstract: A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.

Abstract: A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Abstract: Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

Abstract: A system that includes a machine learning model that is configured to receive an input layout file that includes a portion of an integrated circuit layout that has a previously identified wafer hotspot, match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types, and output a proposed layout modification associated with the matching category of wafer hotspot types.

Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.