Abstract: A detector compares a drain voltage with a first threshold voltage and outputs a first detection signal. An ON-counter detects a period of time during which current flows in a switching circuit based on the first detection signal, counts the period of time based on a predetermined clock cycle, and outputs an ON-count value. A first comparator receives the ON-count value and an ON-threshold value and outputs a first comparison signal when the ON-count value and the ON-threshold value match. A second comparator receives the ON-count value and a decreased ON threshold value, compares the ON-count value and the decreased ON-threshold value, and outputs a second comparison signal. An ON-mask time adjuster receives the second comparison signal and outputs an ON-threshold value for adjusting a mask time and a decreased ON-threshold value that is less than the ON threshold value.

Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A power conversion device according to an embodiment may include: an output circuit configured to perform a power conversion operation of converting input power into an output power and outputting the output power; and a microcomputer configured to control the power conversion operation by the output circuit with power supplied from an internal power source of the output circuit, wherein the microcomputer outputs a status signal notifying whether the microcomputer is in a power shutdown permit period or a power shutdown inhibit period, and the output circuit includes a power supply stop circuit configured, when receiving the operation stop signal that instructs to stop the power conversion operation, to stop the power supply from the internal power source to the microcomputer on a condition where the status signal indicates that the microcomputer is in the power shutdown permit period.

Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region, a second semiconductor region arranged on the first semiconductor region, a third semiconductor region arranged on the second semiconductor region, a first trench penetrating the second semiconductor region from the third semiconductor region and reaching the first semiconductor region, a first main electrode arranged on the second semiconductor region via a first insulating film, field electrodes arranged via second insulating films in a second trenches that are deeper than the first trench and reach the first semiconductor region. The first main electrode may be arranged between the field electrodes. The field electrodes may be arranged alternately, and the field electrodes that are alternately adjacent to each other may be arranged so that the field electrodes partially overlap with adjacent field electrodes in an alignment direction of the arranging field electrodes in a plan view.

Abstract: A first coupling capacitor is electrically connected in series with an input side reactor. A positive rectifier diode is electrically connected in series with the first coupling capacitor. A positive output side reactor is electrically connected to a connecting point of the first coupling capacitor and the positive rectifier diode and a ground potential. A first smoothing capacitor is electrically connected to the positive rectifier diode and a ground potential. A second coupling capacitor is electrically connected in series with the first coupling capacitor. A negative rectifier diode is electrically connected to the positive output side reactor and the second coupling capacitor. A negative output side reactor is electrically connected to a connecting point of the second coupling capacitor and the negative rectifier diode. A second smoothing capacitor is electrically connected to the negative rectifier diode, the ground potential, and the negative output side reactor.

Abstract: A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode. A resistance value of the first resistor may be greater than the second resistor thereof.

Abstract: A semiconductor device according to one or more embodiments may include: on a semiconductor substrate, a high voltage circuit region; a transistor element region; an isolation region that elementally isolates the transistor element region from the high voltage circuit region; and a capacitively coupled field plate including plural lines of conductors, wherein the capacitively coupled field plate is provided to extend circumferentially along an outer circumferential portion of the high voltage circuit region and across the transistor element region, in a plan view of the semiconductor device, and one or more dividing sections divides at least one of the plural lines of conductors in the capacitively coupled field plate to make the at least one line discontinuous.

Abstract: An excitation current detection circuit is disclosed. A transformer comprises a primary winding, an auxiliary winding, and a secondary winding. A first voltage detector detects a positive voltage of an auxiliary winding voltage. A second voltage detector detects a negative voltage of the auxiliary winding voltage. A first voltage controlled oscillator generates a first clock with a frequency proportional to the positive voltage during a period when the auxiliary winding voltage is the positive voltage. A second voltage controlled oscillator generates a second clock with a frequency proportional to the negative voltage during a period when the auxiliary winding voltage is the negative voltage. A counter outputs a counter value, which is added in one of cycles of the first clock and the second clock and subtracted in the other cycle of the first clock and the second clock as a detected value of an excitation current.

Abstract: An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

Abstract: An active clamp flyback converter includes a main switch, a primary winding that is electrically connected in series with the main switch, a clamp switch that is electrically connected to a connection point between the main switch and the primary winding, a clamp capacitor that is connected in series with the clamp switch, and a controller that outputs a first ON signal to control the main switch and a second ON signal to control the clamp switch during a period when the main switch is off. The controller outputs the second ON signal during a half cycle or more of a resonance period, in which the resonance current flowing in a resonance circuit comprising the clamp capacitor and a leakage inductance generated when the clam switch is turned on is limited by an excitation current of an excitation inductance of the primary winding.

Abstract: A direct current to direct current converter is disclosed that controls an output voltage based on an error signal between a feedback voltage and a target voltage. A direct current to direct current converter according to one or more embodiments may include a temperature sensor, a reference voltage generator circuit that generates a reference voltage, a compensation calculator that calculates a compensation value from a temperature detected from the temperature sensor using a function of temperature, a compensator that corrects a target initial value by the compensation value to generate the target value, and a digital-to-analog converter that converts the target value to the target voltage based on the reference voltage.

Abstract: A dimming agent according to one or more embodiments is disclosed that may include at least one of terbium, praseodymium, manganese, titanium. A diffuse reflection intensity of the dimming agent in a wavelength of from 400 nm to 750 nm may be 80% or less.

Abstract: An analog-to-digital converter is disclosed that converts an input analog potential to a digital conversion value. An analog-to-digital converter according to one or more embodiments may include a comparator that compares the input analog potential with a reference potential; and a conversion circuit that measures comparison operation time from a start to an end of a comparison operation by the comparator and outputs the digital conversion value according to the measured comparison operation time and a comparison result by the comparator.

Abstract: A detector compares a drain voltage with a first threshold voltage and outputs a first detection signal. An ON counter detects a period of time during which a current flows in a switching, counts the period of time based on a predetermined clock cycle. An OFF counter detects a period of time during which a current flow through the body diode in a state where no current flows in the switching circuit, counts the period of time. An off-time setting circuit sets the time to turn off the switching circuit. A first comparison circuit compares the cycle count value with turn off time. A second comparison circuit compares a cycle count value output by the ON counter with a comparison result output by the first comparison circuit and outputs a signal to stop transmitting a PWM signal.

Abstract: A detector compares a drain voltage with a first threshold voltage and outputs a first detection signal. An ON-counter detects a period of time during which current flows in a switching circuit based on the first detection signal, counts the period of time based on a predetermined clock cycle, and outputs an ON-count value. A first comparator receives the ON-count value and an ON-threshold value and outputs a first comparison signal when the ON-count value and the ON-threshold value match. A second comparator receives the ON-count value and a decreased ON threshold value, compares the ON-count value and the decreased ON-threshold value, and outputs a second comparison signal. An ON-mask time adjuster receives the second comparison signal and outputs an ON-threshold value for adjusting a mask time and a decreased ON-threshold value that is less than the ON threshold value.

Abstract: A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.

Abstract: A light emitting device according to one or more embodiment is disclosed, which may include a blue LED, a first phosphor that is excited by light of the blue LED and emits green to yellow light, and a second phosphor that is excited by light of the blue LED and emits light with an emission peak wavelength greater than the emission peak wavelength of the first phosphor but 625 nm or less. In one or more embodiments, an emission intensity of the light emitting device at an emission wavelength of 650 nm relative to the emission intensity at the emission peak wavelength of the light emitting device may be 60% or less.

Abstract: A semiconductor device according to one or more embodiment may include: an IGBT region including a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type arranged on the first semiconductor region; a third semiconductor region of the first conductivity type arranged on the second semiconductor region; a fourth semiconductor region of the second conductivity type arranged on the first semiconductor region and opposite the second semiconductor region; and a control electrode that is arranged via an insulating film opposite the second semiconductor region; and a diode region comprising a fifth semiconductor region of the second conductivity type on the first semiconductor region. In the semiconductor device according to one or more embodiments, an impurity concentration of the fifth semiconductor region may be lower than the impurity concentration of the second semiconductor region.

Abstract: An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.

Abstract: A watchdog timer device according to one or more embodiments may include a mode setting unit that sets a first mode or a second mode. In the first mode, the watchdog timer device monitors an operation state of a monitored device and generates an interrupt signal to cause the monitored device to perform recovery processing at a first timeout. In the second mode, the watchdog timer device monitors the recovery processing and generates a reset signal to restart the monitored device at a second timeout. The watchdog timer device uses different logic to execute determining the first timeout in the first mode and determining the second timeout in the second mode.