Patents Assigned to Sanyo Semiconductor Co., Ltd.
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Patent number: 8390212Abstract: A light-emitting-element-driving-control circuit comprising: a control circuit to turn on or off a transistor based on an input-control signal, the transistor being connected in series with a light-emitting element and an inductor connected in series and controlling increase and decrease of a driving current of the light-emitting element; a maximum-value-detection circuit to detect a maximum value of the driving current; and a control-signal-generation circuit to generate the control signal for turning on the transistor to increase the driving current at a speed corresponding to a level of a power-supply voltage when the driving current is smaller than the maximum value and turning off the transistor to be kept for a predetermined period to decrease the driving current at a speed corresponding to a level of a forward voltage of the light-emitting element when the driving current reaches the maximum value, based on a detection result of the maximum-value-detection circuit.Type: GrantFiled: September 23, 2009Date of Patent: March 5, 2013Assignees: Semiconductor Components Industries, LLC;, Sanyo Semiconductor Co., Ltd.Inventor: Tomoaki Nishi
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Patent number: 8377808Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.Type: GrantFiled: March 17, 2011Date of Patent: February 19, 2013Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Yoshimasa Amatatsu
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Patent number: 8374363Abstract: In an amplifier circuit of a capacitor microphone, when a too high input signal from the capacitor microphone is inputted, the levels of output signals of the amplifier circuit are limited. A first feedback capacitor of an operational amplifier is formed using a changeable capacitance type MOS capacitor element, and has a characteristic of increasing the capacitance value CAf1 according to the amplitude of an input signal generated by a capacitor increases. Therefore, CAf (=CAf1+CAF2) increases according to the amplitude of the input signal increases, and accordingly the gain of the operational amplifier decreases, thereby limiting the output signals of the operational amplifier. This realizes the appropriate limitation of the output signals of the operational amplifier, even when the amplitude of the input signal becomes too high.Type: GrantFiled: March 22, 2010Date of Patent: February 12, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Akinobu Onishi
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Patent number: 8373278Abstract: Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different, in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. A process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.Type: GrantFiled: March 14, 2008Date of Patent: February 12, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Hiroyuki Shinogi
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Patent number: 8373197Abstract: Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.Type: GrantFiled: September 28, 2009Date of Patent: February 12, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Kiyoaki Kudo, Takashi Shibasaki, Tetsuya Yamamoto
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Patent number: 8373377Abstract: A shift register which receives a transmission clock signal, which is shifted according to the transmission clock signal, and which outputs a gate signal a predetermined time after reset; a reset circuit which outputs a reset signal for resetting the shift register when the reset circuit receives an input of a step signal for driving the stepping motor; and a switching element which receives the gate signal of the shift register and which is switched between a blocked state and a conductive state are provided in a driving circuit of a stepping motor.Type: GrantFiled: December 17, 2010Date of Patent: February 12, 2013Assignee: Sanyo Semiconductor Co., Ltd.Inventors: Yoshito Motoki, Tsutomu Shimazaki, Yuanjie Wu
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Patent number: 8373246Abstract: Provided is a semiconductor device having an anode of a Si-FRD and a cathode of a Si-SBD which are serially connected. The Si-SBD has a junction capacitance whose amount of accumulable charge is equal to or more than an amount of charge occurring at the time of reverse recovery of the Si-FRD, and has a lower breakdown voltage than the Si-FRD does.Type: GrantFiled: June 16, 2010Date of Patent: February 12, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Seiji Miyoshi, Tetsuya Okada, Shiho Arimoto
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Patent number: 8368181Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: GrantFiled: December 18, 2008Date of Patent: February 5, 2013Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
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Patent number: 8362595Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.Type: GrantFiled: December 18, 2008Date of Patent: January 29, 2013Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
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Patent number: 8350483Abstract: A light-emitting element driving circuit includes a PWM signal output circuit configured to output a plurality of PWM signals each having one logic level whose duty ratio corresponds to gradation data and each corresponding to each of a plurality of light-emitting elements, on the basis of the gradation data indicating brightness of each of the plurality of light-emitting elements. A driving signal output circuit is configured to change the duty ratio of each of the plurality of inputted PWM signals to output the plurality of changed PWM signals as a plurality of driving signals, on the basis of instruction data for changing the brightness of the plurality of light-emitting elements. A driving circuit is configured to drive the plurality of light-emitting elements on the basis of a duty ratio of each of the plurality of driving signals.Type: GrantFiled: December 16, 2009Date of Patent: January 8, 2013Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Takeshi Arai
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Patent number: 8352251Abstract: An audio signal processing circuit is provided which comprises an ADC which samples an audio signal at a predetermined sampling frequency, a high-band compensation processor which compensates a signal sampled by the ADC to a frequency band which is higher than a signal band sampled by the sampling frequency, and an encoding unit which encodes a signal processed by the high-band compensation processor.Type: GrantFiled: October 9, 2009Date of Patent: January 8, 2013Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Kazuhiko Kondo
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Patent number: 8350606Abstract: In a delay circuit for inputting square waves, fluctuations in the amount of delay brought about by noise pulses present in input signals are reduced. A switch (SW3) is controlled by an output signal (Vdo) from a Schmitt comparator, and selects either an electric current source for supplying a charging current to a capacitor (Cst) or an electric current source for supplying a discharging current. A current supply from the selected electric current source is turned on/off by controlling switches (SW1, SW2) using an input signal (Vdi). The Schmitt comparator switches the level of Vdo in accordance with a voltage of Cst. The charging current is supplied to Cst when Vdi is H level at rising edge of Vdi, and the discharging current is supplied to Cst when Vdi is L level at trailing edge of Vdi.Type: GrantFiled: May 10, 2010Date of Patent: January 8, 2013Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Shinji Kurihara
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Patent number: 8344766Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.Type: GrantFiled: November 13, 2007Date of Patent: January 1, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Sadao Yoshikawa, Toshiki Rai
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Patent number: 8344457Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.Type: GrantFiled: February 24, 2010Date of Patent: January 1, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Yasunari Noguchi, Eio Onodera, Hiroyasu Ishida
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Patent number: 8344672Abstract: A differential amplifier detects a coil current Is at the time of steady rotation of a synchronous motor. An application voltage S0 at this time is detected from an output of an ATT circuit and so on. With the use of the coil current Is which is detected, the application voltage S0 at that time, and a predetermined scaling factor As, an induced current Ib is obtained based on Ib=As·S0?Is. The application voltage to the motor is controlled based on the induced current Ib which is obtained.Type: GrantFiled: September 29, 2010Date of Patent: January 1, 2013Assignees: Sanyo Electric Co., Ltd, Sanyo Semiconductor Co., LtdInventor: Kazumasa Takai
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Patent number: 8339860Abstract: This invention offers a semiconductor memory device, with which a resolution to read-out data is not reduced even at the time of verify and a stable read-out operation is possible even when a power supply voltage is reduced. A read-out circuit is provided with a current-voltage conversion circuit, that converts a cell current into a data voltage, and a sense amplifier that compares the data voltage with a reference voltage. The current-voltage conversion circuit is formed to include a variable load resistor that is connected to the memory cell through a bit line. The variable load resistor is formed to include P channel type MOS transistors that make load resistors and P channel type MOS transistors that constitute a switching circuit.Type: GrantFiled: January 21, 2011Date of Patent: December 25, 2012Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Jumpei Maruyama, Sadao Yoshikawa
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Patent number: 8339460Abstract: A video signal processing integrated circuit comprising: a test signal generation circuit configured to generate a test signal in conformity with video additional data superimposed on a video signal; a data slicer configured to binarize the test signal through comparison with a slice level, the test signal being supplied from the test signal generation circuit; and a data processing circuit configured to perform data processing of the video additional data binarized by the data slicer.Type: GrantFiled: May 16, 2008Date of Patent: December 25, 2012Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.Inventors: Shinichi Yamasaki, Masanori Okubayashi, Kazuyoshi Oshima
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Patent number: 8330406Abstract: This invention provides a motor drive circuit, which makes it possible to prevent braking when a power supply voltage is lower than a predetermined voltage while suppressing at a low cost a rise in a voltage on a power supply line when a kickback occurs. The motor drive circuit is formed to include first and second power supply lines connected with and shunted from a power supply, an H-bridge circuit, and a means to control the H-bridge circuit. The means controls the H-bridge circuit so that a regeneration path is not created in the H-bridge circuit when the power supply voltage is lower than a predetermined voltage.Type: GrantFiled: February 23, 2010Date of Patent: December 11, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Joji Noie
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Patent number: 8332448Abstract: The invention reduces unnecessary electromagnetic radiation noise due to an operation clock signal generated by an oscillator circuit. Random number data outputted by a random number generation circuit is stored in a frequency variable data register. The data stored in the frequency variable data register is replaced by random number data sequentially generated by the random number generation circuit. An oscillator circuit is a circuit generating a clock signal, and the clock signal is supplied as an operation clock signal to an internal circuit through an operation clock signal generation circuit. The frequency of the clock signal from the oscillator circuit is variably controlled in response to the random number data stored in the frequency variable data register. A frequency variable range control register which stores control data for controlling the range of the frequency variably controlled in response to the random number data stored in the frequency variable data register is further provided.Type: GrantFiled: October 9, 2008Date of Patent: December 11, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Hideo Kondo
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Patent number: 8327054Abstract: A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for accessing a memory outputs an instruction signal for providing an instruction for starting detection of whether or not data stored in the memory is correct; a data acquisition circuit configured to acquire data stored in the memory through the bus, when the arbitration circuit outputs a permission signal for permitting the occupation of the bus based on the request signal; and a data processing circuit configured to perform processing for detecting whether or not the acquired data is correct, the acquired data acquired by the data acquisition circuit.Type: GrantFiled: June 2, 2010Date of Patent: December 4, 2012Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.Inventor: Naoyuki Ogino