Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.

Abstract: The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.

Abstract: A metal film such as an aluminum film or an aluminum alloy film is etched with good controllability, preventing a resist from bleeding, to have a proper taper configuration and superior flatness. A water solution containing a phosphoric acid, a nitric acid, and an organic acid salt is used as an etching liquid composition used to etch the metal film on a substrate. The organic acid salt is composed of one kind selected from a group consisting of an aliphatic monocarboxylic acid, an aliphatic polycarboxylic acid, an aliphatic oxicarboxylic acid, an aromatic monocarboxylic acid, an aromatic polycarboxylic acid and an aromatic oxycarboxylic acid, and one kind selected from a group consisting of an ammonium salt, an amine salt, a quaternary ammonium salt, and an alkali metal salt. In addition, a concentration of the organic acid salt ranges from 0.1% to 20% by weight.

Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.

Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.

Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.

Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.

Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.

Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.

Abstract: The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N? type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K2 on both sides of a P-type impurity region so that the second openings K2 partially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.

Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.

Abstract: As a discrete semiconductor chip, there has been known one that enables flip-chip mounting by providing first and second electrodes in a current path above a first surface of a semiconductor substrate. However, there is a problem that a horizontal current flow in the substrate increases resistance components. A first electrode and a second electrode, which are connected to an element region, are provided above a first surface. Moreover, a thick metal layer having corrosion resistance and oxidation resistance and also having a low resistance is provided above a second surface. Thus, resistance components of a current flowing in a horizontal direction of a substrate are reduced. Moreover, by appropriately selecting a thickness of the thick metal layer, a resistance value of a device can be reduced while suppressing a cost increase. Furthermore, by adopting Au as the thick metal layer, defects such as discoloration of the thick metal layer with time can be prevented.

Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.

Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.