Abstract: A PASM and TASM encoding method with the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols, and outputting an encoded data bit sequence. The PASM encoding method includes calculating a first set of parity-check symbols from the data-bit sequence along a first set of parity lines, and calculating at least a second set of parity-check symbols from the data symbols and parity-check symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path traversing through the parity-check symbols. The TASM encoding method includes calculating a first parity-check symbol from data symbols and parity-check symbols along a first parity line having a first slope and calculating at least a second parity-check symbol from data symbols and parity-check symbols along a second parity line having a second slope, wherein the second parity line traverses through the first parity-check symbol.

Abstract: A PASM and TASM encoding method is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols, and outputting an encoded data bit sequence. The PASM encoding method includes calculating a first set of parity-check symbols from the data-bit sequence along a first set of parity lines, and calculating at least a second set of parity-check symbols from the data symbols and parity-check symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path traversing through the parity-check symbols. The TASM encoding method includes calculating a first parity-check symbol from data symbols and parity-check symbols along a first parity line having a first slope and calculating at least a second parity-check symbol from data symbols and parity-check symbols along a second parity line having a second slope, wherein the second parity line traverses through the first parity-check symbol.

Abstract: A Schilling-Manela encoding codec is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols from parity-line symbols having p-bits per symbol along parity lines, and setting the parity-check symbols equal to the modulo-2.sup.p sum of the data symbols. The data-bit sequence and parity-check symbols are transformed from Gray symbols, and the Gray symbols are transformed to modulation symbols. A Schilling-Manela decoding method is provided comprising the steps of storing an encoded data-bit sequence in a memory. The encoded-data-bit sequence includes a parity-check-symbol sequence which is stored in parity-memory cells, and a data-bit sequence which is blocked and stored in information-memory cells. The parity-check symbols and the data symbols along the parity lines in the information-memory cells are found.

Abstract: A Schilling-Manela encoding method is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols from parity-line symbols having p-bits per symbol along parity lines, and setting the parity-check symbols equal to the modulo-2.sup.p sum of the parity-line symbols. A Schilling-Manela decoding method is provided comprising the steps of storing an encoded data-bit sequence in a memory. The encoded-data-bit sequence includes a parity-check-symbol sequence which is stored in parity-memory cells, and a data-bit sequence which is blocked and stored in information-memory cells. The parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells are found. The count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error is incremented and the largest-number cell in the composite-error graph having the largest number is determined.

Abstract: A class SM amplifier is provided having a threshold circuit with a plurality of threshold levels for generating a plurality of threshold signals. In response to an input signal passing a particular threshold level, the threshold circuit generates as an output a particular threshold signal. A voltage supply is provided having a plurality of voltage levels. The class SM amplifier includes a plurality of transistors coupled to a load and the threshold circuit, and the plurality of voltage levels from the voltage supply. The transistors switch a particular voltage level across the load in response to a particular threshold signal from the threshold circuit. The plurality of voltage levels are adjusted to approximate the input signal.

Abstract: A class SM amplifier is provided having a threshold circuit with a plurality of threshold levels for generating a plurality of threshold signals. In response to an input signal passing a particular threshold level, the threshold circuit generates as an output a particular threshold signal. A voltage supply is provided having a plurality of voltage levels. The class SM amplifier includes a plurality of transistors coupled to a power combiner and the threshold circuit, and the plurality of voltage levels from the voltage supply. The transistors switch voltage levels across the power combiner in response to a particular threshold signal from the threshold circuit. The power combiner is coupled to a load, and outputs the combination of the voltages from the transistors across the load. The plurality of voltage levels are adjusted to approximate the input signal.