Abstract: In some aspects, an apparatus for encoding data for delivery to or for decoding data retrieved from a storage medium comprises a memory device and at least one hardware processor. The memory device is configured to store at least one parameter associated with at least one cryptographic protocol, the at least one parameter comprising one or more of a first cryptographic scheme, a first cryptographic key operation, a first cryptographic key length, and first cipher directives. The hardware processor is configured to generate a first frame comprising a first field for one parameter selected from the first cryptographic scheme, the first cryptographic key operation, the first cryptographic key length, and the first cipher directives and excluding fields for non-selected parameters, wherein the first frame is associated with the data delivered to or retrieved from the storage medium.
Type:
Grant
Filed:
May 13, 2022
Date of Patent:
May 30, 2023
Assignee:
SeaPort, Inc.
Inventors:
William F. Van Duyne, William Spazante, Gwain Bayley
Abstract: In some aspects, an apparatus for encoding data for delivery to or for decoding data retrieved from a storage medium comprises a memory device and at least one hardware processor. The memory device is configured to store at least one parameter associated with at least one cryptographic protocol, the at least one parameter comprising one or more of a first cryptographic scheme, a first cryptographic key operation, a first cryptographic key length, and first cipher directives. The hardware processor is configured to generate a first frame comprising a first field for one parameter selected from the first cryptographic scheme, the first cryptographic key operation, the first cryptographic key length, and the first cipher directives and excluding fields for non-selected parameters, wherein the first frame is associated with the data delivered to or retrieved from the storage medium.
Type:
Grant
Filed:
September 12, 2019
Date of Patent:
May 17, 2022
Assignee:
SEAPORT, INC.
Inventors:
William F. Van Duyne, William Spazante, Gwain Bayley
Abstract: In some aspects, an apparatus for encoding data for transmission by a transmitter device to a receiver device having an initial common cryptographic key with the apparatus comprises a memory device and a hardware processor. The memory device is configured to store a plurality of parameters associated with a plurality of cryptographic protocols, the plurality of parameters comprising the initial common cryptographic key. The hardware processor is configured to generate a frame comprising a plurality of fields defining instructions related to a first cryptographic scheme, a first cipher directive, a first cryptographic key operation, and/or a first cryptographic key length, that are derived from the plurality of parameters for use in a subsequent communication session with the receiver device.
Abstract: In some aspects, an apparatus for encoding a stream of data for transmission to a receiver device comprises a memory device and a hardware processor. The memory device is a memory device configured to store at least one parameter associated with at least one cryptographic protocol, the at least one parameter identifying one or more cipher directives from a plurality of cipher directives including an exclusive-OR (XOR) function and a table lookup function. The hardware processor is configured to generate, for transmission to the receiver device, a frame comprising a first field identifying a custom or non-custom cryptographic scheme and a second field identifying a first cipher directive of the plurality of cipher directives.
Type:
Grant
Filed:
September 12, 2019
Date of Patent:
September 14, 2021
Assignee:
SeaPort, Inc.
Inventors:
Gwain Bayley, William F. Van Duyne, William Spazante
Abstract: In some aspects, an apparatus for encoding data for transmission to a receiver device having an initial common cryptographic key with the apparatus comprises a memory device and a hardware processor. The memory device is configured to store a plurality of parameters associated with a plurality of cryptographic protocols, the plurality of parameters comprising the initial common cryptographic key. The hardware processor is configured to generate a frame comprising a plurality of fields defining instructions related to one or more of a first cryptographic scheme, a first cryptographic key operation, and a first cryptographic key length that are derived from the plurality of parameters for use in a subsequent communication session with the receiver device.