Abstract: An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.

Abstract: In a 100BASE-T4 protocol network, the "carrier.sub.-- status" signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.

Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.

Abstract: The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.

Abstract: The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry.

Abstract: A downward compatible full-duplex ethernet transceiver associated with either the hub or the remote node in an ethernet local area network (LAN) includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over a link of the LAN and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the link of the LAN. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of from about 2 to about 7 microseconds.

Abstract: A one pin on-chip crystal oscillator circuit and a method of operating that oscillator are provided. The oscillator makes use of the gate-source capacitance of a MOS transistor to provide capacitance which would otherwise need to be provided by one of two oscillator capacitors. The MOS transistor is provided with a floating well by coupling its body to its source, so that the gate-source capacitance does not change substantially when the transistor is turned off. In another aspect of the invention, the MOS transistor is provided with a floating well using a parallel combination of MOS transistor elements, so as to minimize the coupling resistance of the MOS transistor to other elements of the circuit.

Abstract: A downward compatible full-duplex 10Base-T ethernet transceiver associated with both the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.

Abstract: A downward compatible full-duplex 10Base-T ethernet transceiver associated with either the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.

Abstract: An apparatus for page mode programming of an EEPROM cell array with false loading protection is disclosed. The system includes a flip-flop operatively connected to a bit line for storing information to be loaded into an EEPROM memory cell, and false loading protection circuitry operatively connected to the bit line for preventing the false loading of an erroneous signal into the flip-flop and/or an EEPROM cell.

Abstract: A fault tolerant memory and method for sensing is disclosed. A pair of memory cells each including a memory device and a select device are connected to a pair of bit lines. The bit lines are connected through select devices to a differential sense amplifier. Each pair of memory cells stores a single bit of data; the first memory cell stores the data bit and the second memory cell stores the compliment of the data bit. The memory cells are fabricated such that they exhibit three states; a first state in which they conduct current, a second state in which they do not conduct current, and a third, abnormal, state into which they fail wherein they conduct approximately half of the current which would be conducted in the first state.

Abstract: A control circuit for erasing EEPROM memory cells is disclosed, including a charge pump having two switched constant current sources driven by opposing clocks. Current produced by the current sources is coupled to a node from where it is used to erase EEPROM memory cells. A switch is provided to isolate the device being erased by floating its source.

Abstract: The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line.A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together.

Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.

Abstract: An apparatus for page mode programming of a memory cell with false loading protection is disclosed. The apparatus discharges any residual voltage left on the bit line after a read operation to prevent this voltage from being erroneously loaded into temporary storage apparatus associated with the bit line. In a preferred embodiment, two transistors are placed in series between the bit line and the array V.sub.ss line. A first transistor is controlled by a signal indicating that information is to be loaded into the temporary storage apparatus. The second transistor is controlled by a signal indicating that no memory cell associated with the bit line has been selected for programming.

Abstract: An electrically programmable, electrically erasable semiconductor memory apparatus for storing information in which the equivalent of a floating gate memory device and a select transistor device are combined in a single device cell is disclosed. A single control gate both controls a select transistor and is used in programming the floating gate.

Abstract: A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, so that a failed bit appears as if unprogrammed or erased. Because each bit is represented by a pair of memory cells, a failed cell in a pair will not affect operation of the functioning cell in the pair or result in error.

Abstract: Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the present invention. The sense amplifier tolerates increased variation in the characteristics of programmed or unprogrammed cells and therefore increases the manufacturing yields of the arrays. It additionally achieves fast accessing and sensing of the stored data.

Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.