Patents Assigned to SEH America
  • Patent number: 7229601
    Abstract: A process for reclaiming ammonia from waste streams comprises reacting at least one waste stream with an excess of hydroxide to produce ammonia and water. The ammonia is removed from the reaction vessel and purified.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: June 12, 2007
    Assignee: SEH-America, Inc.
    Inventor: Brian L. Tansy
  • Patent number: 7196009
    Abstract: A method of fabricating a lapping carrier is provided that includes the steps of defining at least one opening extending through a workpiece that is sized to receive a wafer, and cryogenically tempering the workpiece to produce a lapping carrier. By cryogenically tempering the workpiece, the conversion of the crystalline structure of the workpiece to a martensite crystalline structure is enhanced, thereby improving the hardness of the lapping carrier. A lapping carrier is also provided that has a crystalline structure, of which at least 70% is a martensite crystalline structure. An apparatus for lapping a wafer is further provided that includes a hardened lapping carrier and at least one lapping plate proximate the lapping carrier for lapping wafer(s) disposed within the at least one opening defined by the lapping carrier.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 27, 2007
    Assignee: SEH America, Inc.
    Inventors: Brian L. Bex, David K. Chen
  • Patent number: 7137405
    Abstract: A check valve for preventing backflow of media including a valve movably coupled to a carrier body, the valve including a flexible membrane disposed therein such that the flexible membrane flexibly engages an aperture in the carrier body to prevent backflow of media through the aperture.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: November 21, 2006
    Assignee: SEH America, Inc.
    Inventors: Richard F. Barrows, Mike Hamilton
  • Patent number: 7112509
    Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: September 26, 2006
    Assignees: Ibis Technology Corporation, SEH America, Inc.
    Inventors: Yuri Erokhin, Okeg V. Konochuk
  • Patent number: 7059943
    Abstract: A slurry recycling apparatus having a first filter, a dirty side storage tank, slurry pump, second filter, clean side storage tank and slurry outlet, in which used slurry from an edge notch polishing apparatus is delivered to the first screen filter, transported to the dirty side slurry storage tank, pumped from the dirty side slurry storage tank through a second filter that filters out small particulate matter from the slurry and allows the slurry to pass to the clean side slurry storage tank, and finally to the edge notch polishing apparatus as needed. Slurry which is not immediately taken from the clean side slurry storage tank is continuously recycled through the second filter by overflowing from the clean side to the dirty side slurry storage tank where it is there pumped through the second filter back into the clean side slurry storage tank.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: June 13, 2006
    Assignee: SEH America, Inc.
    Inventors: Scott Cann, Michael Huston, Sergey N. Altukhov
  • Publication number: 20050229857
    Abstract: A support fixture is provided that includes a boat, a first layer deposited on at least a portion of the boat that has fewer impurities than the boat, and a second layer deposited on at least a portion of the first layer that is formed of a material having one or both of a hardness and a coefficient of thermal expansion that more closely matches the material properties of the wafers to be carried by the support fixture than does those of the boat and the first layer. For example, the boat and the first layer may be formed of silicon carbide and the second layer may be formed of polysilicon. A method of fabricating a support fixture having a boat coated with first and second layers, such as by sequential chemical vapor deposition steps, is also provided.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 20, 2005
    Applicant: SEH America, Inc.
    Inventors: David Beauchaine, Aaron Newton
  • Publication number: 20050175523
    Abstract: A process for reclaiming ammonia from waste streams comprises reacting at least one waste stream with an excess of hydroxide to produce ammonia and water. The ammonia is removed from the reaction vessel and purified.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 11, 2005
    Applicant: SEH-AMERICA, INC.
    Inventor: Brian Tansy
  • Patent number: 6896727
    Abstract: An improved method of determining the concentration of nitrogen within a wafer is provided. At least a portion of the nitrogen within the wafer is initially gettered to a gettering site. In order prevent the in-diffusion of nitrogen, a barrier layer is generally deposited upon the wafer prior to gettering the nitrogen within the wafer. The nitrogen is then measured at the gettering site. The concentration of nitrogen within the wafer is then determined based upon the measurement of nitrogen at the gettering site and the diffusion coefficient for nitrogen. In this regard, the diffusion coefficient of nitrogen permits the measurement of nitrogen at the gettering site to be translated into a measurement of the concentration of nitrogen throughout the entire wafer.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 24, 2005
    Assignee: SEH America, Inc.
    Inventor: Sergei V. Koveshnikov
  • Patent number: 6889684
    Abstract: The apparatus, system and method for cutting crystal ingot provide techniques for cutting an ingot into wafers with a wire cutting apparatus utilizing wire with a diameter of less than 0.18 mm, such as 0.14 mm. The wire cutting apparatus also includes multiple rollers about which the wire is wrapped, and nozzles for applying slurry to the wire. One of the rollers is located on one side of the crystal ingot, while another roller is located on the other side of the crystal ingot. At least one nozzle is disposed proximate the first and second rollers. The nozzles collectively disperse slurry at a rate in the range of 40 to 60 liters per minute, such as 50 liters per minute, and at a viscosity of 42 to 62 centipose, such as 52 centipose.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: May 10, 2005
    Assignee: SEH America, Inc.
    Inventors: Shawn V. McAulay, Kazuhisa Takamizawa
  • Publication number: 20050053535
    Abstract: A method and apparatus are provided for removing oxygen and moisture from a gas such that wafers subsequently exposed to the gas develop less haze. The apparatus includes a process chamber for receiving a wafer. The apparatus also includes a gettering filter in fluid communication with the process chamber for removing oxygen from a gas that passes through the gettering filter in route to the process chamber. The gettering filter includes a vessel and a plurality of pieces of an oxidizable material disposed within the vessel. The oxidizable material is selected to oxidize upon exposure to oxygen in the gas such that the gas exiting the vessel has less oxygen than the gas entering the vessel. The oxidizable material may also be selected such that the resulting oxide layer is etchable upon exposure to an etchant, thereby permitting the gettering filter to be regenerated.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 10, 2005
    Applicant: SEH America, Inc.
    Inventors: David Beauchaine, Oleg Kononchuk
  • Patent number: 6849548
    Abstract: A method of polishing the surface of a semiconductor wafer such that the adherence of abrasive particles to the surface of the wafer is minimized, resulting in a semiconductor wafer having a reduced number of pits. The invented method has two stages. The first stage follows traditional polishing practice using chemical mechanical polishing. The second stage diverges from traditional practices and provides for a final polishing step or steps involving the polishing of the wafer with a polishing solution having no abrasive particles.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: February 1, 2005
    Assignee: SEH America, Inc.
    Inventor: Steven P. Cooper
  • Patent number: 6825487
    Abstract: A method of measurement of wafers to isolate wafer support-related defects involves Scanning Infrared Depolarization (SIRD) measurement of multiple processed wafers, each oriented differently on the wafer support, to obtain and characterize depolarization stress defects. The method mounts first and second wafers in first and second orientations and performs a SIRD scan of each. The results are correlated to isolate orientation dependent defects from non-orientation dependent defects. Orientation dependent defects are characterized as wafer support-related defects. Analysis of such wafer support-related defects may then be used to identify and correct the corresponding wafer support defect.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 30, 2004
    Assignee: Seh America, Inc.
    Inventor: Brazel G. Preece
  • Publication number: 20040224477
    Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Applicants: IBIS TECHNOLOGY CORPORATION, SEH AMERICA, INC.
    Inventors: Yuri Erokhin, Oleg V. Kononchuk
  • Publication number: 20040224522
    Abstract: A method of fabricating a lapping carrier is provided that includes the steps of defining at least one opening extending through a workpiece that is sized to receive a wafer, and cryogenically tempering the workpiece to produce a lapping carrier. By cryogenically tempering the workpiece, the conversion of the crystalline structure of the workpiece to a martensite crystalline structure is enhanced, thereby improving the hardness of the lapping carrier. A lapping carrier is also provided that has a crystalline structure, of which at least 70% is a martensite crystalline structure. An apparatus for lapping a wafer is further provided that includes a hardened lapping carrier and at least one lapping plate proximate the lapping carrier for lapping wafer(s) disposed within the at least one opening defined by the lapping carrier.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Applicant: SEH America, Inc.
    Inventors: Brian L. Bex, David K. Chen
  • Publication number: 20040213376
    Abstract: The method and apparatus of the present invention permit indirect identification of a target plane, such as the plane identified by an alignment feature, based upon the identification of a reference plane which is offset by a predetermined angle from the target plane. In addition, in order to permit alignment features to be defined at non-standard angles with respect to the axial orientation of an ingot, an apparatus is provided that includes a frame having at least two members. The first member abuts a bar extending outwardly from the stage of an x-ray diffractometer, while the second member carries an engagement member for engaging a non-standard alignment feature. The second member may be movable relative to the first member to permit the frame to be mounted upon ingots having different non-standard alignment features.
    Type: Application
    Filed: May 17, 2004
    Publication date: October 28, 2004
    Applicant: SEH America, Inc.
    Inventors: Richard M. Aydelott, Mark E. Secrest
  • Patent number: 6808564
    Abstract: A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. At least one epitaxial layer surface is substantially hydrophobic. Then, a chemical reagent is introduced into said epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer layer.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: October 26, 2004
    Assignee: SEH America, Inc.
    Inventor: Gerald R. Dietze
  • Patent number: 6798526
    Abstract: Methods and apparatus for predicting the density of oxygen-induced stacking faults (OSF) on a surface of a wafer by measuring the surface roughness before and after a surface damaging process is presented. Such damage can be produced by, but not limited to, a wet sand blast (WSB) process, a dry sand blast (DSB) process, lapping with an abrasive material, surface grinding, and by laser irradiation. The surface roughness resulting from the surface damage is quantified and compared with the pre-damaged surface roughness. The difference between the pre- and post-damaged surface roughness is determined and correlated with oxygen-induced stacking fault density to surface roughness correlation data to obtain the predicted oxygen-induced stacking fault density.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: September 28, 2004
    Assignee: SEH America, Inc.
    Inventors: Timothy L. Brown, Dorothy E. Goff, Romony K. San
  • Patent number: 6794227
    Abstract: A semiconductor wafer manufacturing is disclosed wherein an SOI wafer is produced by annealing a polysilicon layer deposited on a substrate wafer in an oxygen-containing ambient, and annealing the wafer at high temperatures to form an oxide layer at the interface of the substrate wafer and polysilicon layer. During the high temperature anneal, the polycrystalline silicon layer also recrystallizes to a monocrystalline state, and replicates the lattice structure of the substrate wafer.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: September 21, 2004
    Assignee: SEH America, Inc.
    Inventor: Sergei V. Koveshnikov
  • Publication number: 20040176916
    Abstract: A system and method are provided for collecting, storing, and displaying a plurality of different types of process data, including accumulated and differential particle counts, from remote locations without requiring manual intervention. The system includes a plurality of particle measuring instruments disposed at respective locations distributed about a facility in order to collect particle data. The system also includes a process data collection device for providing process data other than particle data, such as temperature, pressure or humidity level. The system is interconnected with the plurality of particle measuring instruments and the process data collection device by means of a computer network. As such, the particle data and process data can be provided to a computer network for collection and storage. Thereafter, the particle data and the process data can be remotely displayed at a graphic user interface.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 9, 2004
    Applicant: SEH America, Inc
    Inventors: Michael M. Robinson, Leif Carlson
  • Publication number: 20040157461
    Abstract: A method for fabricating a wafer including an improved method for processing the edge of a wafer that utilizes dry etching techniques is provided. In this regard, the profile of the edge of the wafer may initially be defined, such as by rounding or chamfering the edge of the wafer. The wafer edge may then be dry etched, such as by atmospheric downstream plasma (ADP) etching, chemical downstream etching (CDE) or the like, in order to smooth the edge of the wafer while eliminating, or reducing, the use of wet chemical etchants. In addition, one or both major surfaces of the wafer may be dry etched, also with ADP etching or CDE, to further reduce the use of wet chemical etchants. Wafers fabricated according to this method are also provided.
    Type: Application
    Filed: February 10, 2003
    Publication date: August 12, 2004
    Applicant: SEH America, Inc.
    Inventors: Oleg V. Kononchuk, Yi Pan, Brazel G. Preece