Abstract: An electronic timepiece without system failure at the time of transfer from the power-saving mode to the display mode is provided. A power-saving control circuit 400 controls drive of a date dial displaying a date when updating a date display, which has been stopped in a power-saving mode, to a current date at the time of transfer from the power-saving mode to the display mode. The power-saving control circuit 400 outputs a date dial drive inhibiting signal, which prohibits drive of the date dial 75, to a date-updating control circuit 300, if a voltage VDD of a power source unit B is less than or equal to a low threshold voltage V1. It outputs a date dial deceleration driving signal, which drives a date dial 75 with a predetermined speed slower than a normal update speed when transferring to the display mode, to a date-updating control circuit 300, if a source voltage VDD is equal to or less than a high threshold voltage V2.