Abstract: Provided are methods of fabricating a semiconductor structure. The methods include providing a III-V semiconductor substrate selected from InGaAs and InAs, introducing an n-type dopant selected from S, Se, and Te directly onto a surface of the III-V semiconductor substrate, introducing a co-dopant selected from N and P directly onto a surface of the III-V semiconductor substrate, and diffusing the n-type and co-dopant into the III-V semiconductor substrate, thereby forming an n-doped III-V semiconductor substrate containing the n-type dopant and the co-dopant. The methods produce inventive semiconductor structures, and devices that include the semiconductor structure.

Abstract: A process for abrasive-free chemical mechanical planarization of silicon thin film coated EUV mask substrates is disclosed. The process removes bumps and pits on the substrate thereby mitigating reflective errors in the mask. The process employs a two-step polishing procedure, in which the second step is abrasive-free and uses an amine or amine salt as the polishing agent.

Abstract: An apparatus, system, and method for cleaning surfaces is presented. One embodiment of the system includes an array of surface acoustic wave (SAW) transducers coupled to a substrate. The system may include a positioning mechanism coupled to at least one of a target surface or the array of SAW transducers, and configured to position the array of SAW transducers within an effective cleaning distance of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of SAW transducers to the target surface. The system may further include a controller coupled to the array of SAW transducers and configured to activate the array of SAW transducers. At least one of the SAW transducers may be formed to focus cleaning liquid on a focal point and jet cleaning liquid in a direction substantially out of the place of the SAW transducer.

Abstract: A cleaning tool facilitating removal of particles from a surface is provided which includes an acoustic wave generator and one or more light-emitting diodes. The acoustic wave generator, which is configured to direct acoustic waves towards the surface to be cleaned, may include an acoustic transducer that facilitates generating the acoustic waves, and an acoustic coupler substrate through which the acoustic waves propagate. The light-emitting diode(s), which is configured to direct light towards the surface to be cleaned, is coupled to the acoustic coupler substrate of the acoustic wave generator. The acoustic wave generator and the light-emitting diode(s) are spaced from the surface to be cleaned, and are configured to selectively concurrently direct overlapping, at least partially, acoustic waves and light energy towards the surface to facilitate removal of particles by breaking bonds between the particles and the surface.

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract: The present invention includes methods directed to improved processes for producing a monolayer of sulfur or selenium on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.

Abstract: Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 ?/sq.

Abstract: An apparatus is provided for protecting a surface of interest from particle contamination, and particularly, during transitioning of the surface between atmospheric pressure and vacuum. The apparatus includes a chamber configured to receive the surface, and a protector plate configured to reside within the chamber with the surface, and inhibit particle contamination of the surface. A support mechanism is also provided suspending the protector plate away from an inner surface of the chamber. The support mechanism holds the protector plate within the chamber in spaced, opposing relation to the surface to provide a gap between the protector plate and the surface which presents a diffusion barrier to particle migration into the gap and onto the surface, thereby inhibiting particle contamination of the surface.

Abstract: An apparatus is provided for protecting a surface of interest from particle contamination, and particularly, during transitioning of the surface between atmospheric pressure and vacuum. The apparatus includes a chamber configured to receive the surface, and a protector plate configured to reside within the chamber with the surface, and inhibit particle contamination of the surface. A support mechanism is also provided suspending the protector plate away from an inner surface of the chamber. The support mechanism holds the protector plate within the chamber in spaced, opposing relation to the surface to provide a gap between the protector plate and the surface which presents a diffusion barrier to particle migration into the gap and onto the surface, thereby inhibiting particle contamination of the surface.

Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.

Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

Abstract: A deposition chamber shield having a stainless steel coating of from about 100 microns to about 250 microns thick wherein the coated shield has a surface roughness of between about 300 microinches and about 800 microinches and a surface particle density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles below about 1 micron in size, and process for production thereof is disclosed.

Abstract: A process for cleaning and restoring deposition shield surfaces which results in a cleaned shield having a surface roughness of between about 200 microinches and about 500 microinches and a particle surface density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles less than about 1 micron in size and method for use thereof is disclosed.

Abstract: Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations.

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

Abstract: An alternating phase shift mask for use with extreme ultraviolet lithography is provided. A substrate with a planar top surface is used as a base for the phase shift mask. A spacer layer serves as a Fabry-Perot cavity for controlling the phase shift difference between two adjacent surfaces of the phase shift mask and controlling the reflectivity from the top of the second multilayer. A protective layer serves as an etch stop layer to protect a first multilayer region in certain regions of the phase shift mask, while other regions of the phase shift mask utilize a second multilayer region for achieving a phase shift difference. Some embodiments may further include an absorber layer region to provide areas with no reflectance, in addition to the areas of alternating phase shift. Embodiments of the present invention may be used to monitor the focus and aberration of a lithography tool.

Abstract: Apparatuses and methods are provided for electrostatically inhibiting particle contamination of a surface of a process structure, such as a mask or reticle. The apparatuses include a plasma-generating system configured to establish a plasma shield over the surface of the process structure. The plasma shield includes a plasma region and a plasma sheath over the surface of the process structure, with the plasma sheath being disposed, at least partially, adjacent to the surface of the process structure, between the plasma region and the surface of the process structure. The plasma shield facilitates negatively charging particles within the plasma shield, and electrostatically inhibits negatively-charged particle contamination of the surface of the process structure to be protected.

Abstract: A process for cleaning and restoring deposition shield surfaces which results in a cleaned shield having a surface roughness of between about 200 microinches and about 500 microinches and a particle surface density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles less than about 1 micron in size and method for use thereof is disclosed.

Abstract: A deposition chamber shield having a stainless steel coating of from about 100 microns to about 250 microns thick wherein the coated shield has a surface roughness of between about 300 microinches and about 800 microinches and a surface particle density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles below about 1 micron in size, and process for production thereof is disclosed.