Abstract: In a general aspect, a power module package includes a substrate that has a ceramic layer with a first primary surface and a second primary surface opposite the first primary surface. The substrate also includes a patterned metal layer disposed on the first primary surface. The package also includes a first plurality of semiconductor die disposed on a first portion of the patterned metal layer. The first plurality of semiconductor die are linearly arranged along a first axis. The package further includes a second plurality of semiconductor die disposed on a second portion of the patterned metal layer. The second plurality of semiconductor die are linearly arranged along a second axis parallel to the first axis.

Abstract: In a general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface; a semiconductor die coupled with the first surface of the die attach paddle, and a direct-bonded-metal (DBM) substrate The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface, a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle, a second metal layer disposed on the second surface of the ceramic layer, and a thermally conductive adhesive disposed on the second metal layer, At least a surface of the thermally conductive adhesive can be exposed external to the device package. The thermally conductive adhesive can be configured for coupling the device package with a thermal dissipation appliance.

Abstract: A package includes a frame having a cooling fluid channel therethrough. The frame has at least one opening in a first sidewall alongside the cooling fluid channel and at least one opening in a second sidewall alongside the cooling fluid channel. A first power electronics module covers the at least one opening in the first sidewall with a surface of a substrate in the first power electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the first sidewall, and a second power electronics module covers the at least one opening in the second sidewall with a surface of a substrate in the second electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the second sidewall.

Abstract: Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, an isolation structure may be formed in a ring around the SPAD. The isolation structure may be a hybrid isolation structure with both a metal filler that absorbs light and a low-index filler that reflects light. The isolation structure may be formed as a single trench or may include a backside deep trench isolation portion and a front side deep trench isolation portion. The isolation structure may also include a color filtering material.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

Abstract: Various embodiments of the present technology may provide methods and apparatus for region of interest histogramming. The apparatus may use a state machine in conjunction with a memory to generate a first histogram having a fixed number of bins over a first range and generate a second histogram having the fixed number of bins over a region of interest selected based on the first peak of the first histogram.

Abstract: Provided herein is a digital communications bus suitable for automotive applications, along with bus controllers and sensors that use the bus and its associated communication methods. One illustrative sensor includes: a clock signal generator; a bus interface coupled to differential signal conductors to detect periodic synchronization pulses from a bus controller; and a controller that aligns a clock signal from the clock signal generator with the periodic synchronization pulses. The bus interface sends digital data between the periodic synchronization pulses to the bus controller using the clock signal to control symbol transitions.

Abstract: Various sensors, sensor controllers, and sensing methods are suitable for use in a multi-channel ultrasonic sensor array such as those used in systems for parking assistance, blind spot monitoring, and driver assistance. One illustrative acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including an up-chirp in a first frequency band and a down-chirp in a second frequency band; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer. Another acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including a concurrent up-chirp and down-chirp; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer.

Abstract: Disclosed sensors, sensor controllers, and sensor control methods enhance transducer performance using a model-based equalization method that can be performed in the field. One illustrative method for operating a piezoelectric-based sensor includes: sensing a response of a piezoelectric transducer as a function of frequency; deriving parameter values of an equivalent circuit for the piezoelectric transducer from the response; using a squared magnitude of the equivalent circuit's transfer function to determine a system level selectivity; and adapting at least one operating parameter of the sensor based on the system level selectivity. One illustrative controller for a piezoelectric transducer includes: a transmitter that drives the piezoelectric transducer; a receiver that senses a response of the piezoelectric transducer; and a processing circuit coupled to the transmitter and to the receiver to calibrate the transducer using the foregoing method.

Abstract: A semiconductor device may include a plurality of single-photon avalanche diodes. The single-photon avalanche diodes may be arranged in microcells. Each microcell may be a split microcell with first and second independent microcell segments. Each microcell segment in the split microcell may have a respective single-photon avalanche diode that is coupled to an output line. The single-photon avalanche diode of each microcell segment may also be coupled to a respective resistor that is used to quench avalanches in the single-photon avalanche diode. Splitting the microcell may reduce the recovery time of each microcell. The segments of the split microcell may be positioned close together, even if susceptible to optical crosstalk. Intra-microcell isolation structures may be formed between the microcell segments. Inter-microcell isolation structures may be formed around a perimeter of the split microcell. The intra-microcell and inter-microcell isolation structures may be different.

Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

Abstract: An imaging system may include an electronic shutter. The electronic shutter may be positioned between an image sensor and a lens module or may be integrated as a package cover for the image sensor. The electronic shutter may selectively attenuate incident light that passes to the image sensor. To increase the dynamic range of the imaging system, the electronic shutter may have a first transparency while a first image is captured by the image sensor and a second, different transparency while a second image is captured by the image sensor. The first and second images are subsequently combined to form a single high dynamic range image. The electronic shutter may be controlled at a global level, at a sub-array level, or at a pixel level.

Abstract: A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.

Abstract: A crucible for manufacturing semiconductor crystals may be disposed adjacent to a heating element. The crucible may include a first seed crystal site and a second seed crystal site at opposed ends of the crucible. A compartment may be defined between an outer wall and an inner wall of the crucible, where the inner wall is formed with a porous graphite membrane. Source powder loaded into the compartment may then be heated by the heating element to sublimate and diffuse from the compartment and through the inner wall to provide crystal growth of a first seed crystal at the first seed crystal site and of a second seed crystal at the second seed crystal site.

Abstract: A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

Abstract: An integrated circuit package (34, 34?, 34?) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).

Abstract: A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.

Abstract: Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.