Patents Assigned to Semiconductor Energy Laborartory Co., Ltd.
  • Patent number: 9543445
    Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ?r/d is greater than or equal to 0.08 (nm?1) and less than or equal to 7.9 (nm?1) when the relative permittivity of a material used for the gate insulating layer is ?r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 ?m.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 10, 2017
    Assignee: Semiconductor Energy Laborartory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Daisuke Kawae
  • Patent number: 6410374
    Abstract: A method of fabricating MIS transistors starts with formation of gate electrode portions. Then, high-speed ions are irradiated through an insulating film to implant impurity ions into a semiconductor region by a self-aligning process, followed by total removal of the insulating film. The laminate is irradiated with laser light or other similar intense light to activate the doped semiconductor region. Another method of fabricating MIS transistors begins with formation of a gate-insulating film and gate electrode portions. Then, the gate-insulating film is removed, using the gate electrode portions as a mask. The semiconductor surface is exposed, or a thin insulating film is formed on this surface. High-speed ions are irradiated to perform a self-aligning ion implantation process. A further method of fabricating MIS transistors starts with formation of a gate-insulating film and gate electrode portions.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: June 25, 2002
    Assignee: Semiconductor Energy Laborartory Co., Ltd.
    Inventor: Shunpei Yamazaki