Abstract: A semiconductor device and a manufacturing method therefor are provided. The semiconductor device includes a semiconductor substrate including a trench used for a source/drain region; and a SiGe seed layer formed simultaneously on the sidewall and bottom of the trench, and the SiGe seed layer on the sidewall of the trench has an uneven thickness with a maximum thickness at a location corresponding to the channel region in the semiconductor substrate. The semiconductor device and the manufacturing method therefor according to the present disclosure enable the SiGe seed layer to block diffusion of elements such as boron more effectively.

Abstract: An interface device may include a first transistor, a pull-up unit, a pull-down unit, a first power supply terminal, a ground terminal, an output signal terminal, and a bias unit. A first gate terminal of the pull-up unit is electrically connected to a source terminal of the first transistor. A drain terminal of the pull-down unit is electrically connected to a drain terminal of the first transistor. The first power supply terminal is electrically connected to a source terminal of the pull-up unit. The ground terminal is electrically connected to a source terminal of the pull-down unit. The output signal terminal is electrically connected to each of a drain terminal of the pull-up unit and the drain terminal of the pull-down unit. An output terminal of the bias unit is electrically connected, without any intervening transistor, to a gate terminal of the first transistor.

Abstract: An integrated circuit includes a semiconductor substrate, and at least two transistors connected in series on the semiconductor substrate, wherein each transistor shares a source electrode or a drain electrode with an adjacent transistor. The integrated circuit also includes a hermetic cavity disposed on the source electrode and the drain electrode, between gate electrodes of adjacent transistors. The source electrode disposed at a first end portion of the series of transistors is in direct contact with a source interconnect, and the drain electrode disposed at a second end portion of the series of transistors is in direct contact with a drain interconnect.

Abstract: An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.

Abstract: A standard wafer is provided including a substrate; a first layer of semiconductor material formed on the substrate; a bar formed over the first layer of semiconductor material with an interlayer interposed therebetween; and a first sidewall spacer and a second sidewall spacer formed on the opposite sides of the bar respectively, in which the bar and the first layer of semiconductor material are formed of a same semiconductor material, and the interlayer interposed between the first layer of semiconductor material and the bar is formed of a first oxide, and the first sidewall spacer and the second sidewall spacer are formed of a second oxide. A corresponding fabrication method of the standard wafer is also provided.

Abstract: A laser annealing device for compensating wafer heat maps and its method are disclosed. A laser annealing device comprises a pump laser source array including of a plurality of pump laser sources for irradiating a tunable mask, each pump laser source emitting pump laser, an annealing laser source for emitting annealing laser and irradiating the tunable mask, and a tunable mask for transmitting at least part of the annealing laser after being irradiated by the pump laser.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.

Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.