Patents Assigned to Semiconductor Manufacturing International (Shanghai) Corporation
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Publication number: 20230402316Abstract: The present disclosure relates to a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a first wafer, including a first substrate and a first dielectric layer on the first substrate, a pad groove and a pad structure in the pad groove are formed in the first substrate and the first dielectric layer, and the pad groove extends through the first substrate along a direction from the first substrate to the first dielectric layer and extends into a partial thickness of the first dielectric layer; and an isolation ring structure, arranged in the first substrate around the pad groove and extending through the first substrate along the direction from the first substrate to the first dielectric layer.Type: ApplicationFiled: May 26, 2023Publication date: December 14, 2023Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Bingquan WANG, Siriguleng Zhang, Dayong Yan, Zhigao Wang, Daming Zhang
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Patent number: 11837497Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, including a plurality of protrusions; a plurality of fins formed over the substrate and aligned with the plurality of protrusions; and an isolation structure formed on the substrate and between the protrusions and the fins. An orthographic projection of each of the plurality of fins and an orthographic projection of a corresponding protrusion of the plurality of protrusions on the substrate coincide with each other.Type: GrantFiled: September 10, 2021Date of Patent: December 5, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Nan Wang
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Publication number: 20230387161Abstract: A photoelectric sensor and a method for forming same and an electronic device are provided. The photoelectric sensor includes: a base, having a light receiving surface and including a pixel unit region; and a plurality of light trapping grooves, arranged in a part of the base in a thickness direction in the pixel unit region and arranged on a side of the light receiving surface of the base, where a surface shape of each of the light trapping grooves is arcuate. The present disclosure helps improve photosensitive performance of the photoelectric sensor.Type: ApplicationFiled: October 11, 2022Publication date: November 30, 2023Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Hongmin LIU, Qiangwei CUI, Changcheng GAO
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Patent number: 11830921Abstract: A semiconductor structure and a fabrication method thereof. The semiconductor structure, includes a substrate; and a work function layer on the substrate, that the work function layer contains aluminum and oxygen elements, the work function layer includes a first surface and a second surface opposite to the first surface, a distance between the first surface and a surface of the substrate is less than a distance between the second surface and the surface of the substrate, and along a direction from the first surface to the second surface, a molar percentage concentration of aluminum atoms in the work function layer decreases, and a molar percentage concentration of oxygen atoms in the work function layer decreases. The semiconductor structure can improve the ability to adjust the threshold voltage of a device, thereby improving the performance of the formed semiconductor structure.Type: GrantFiled: August 6, 2021Date of Patent: November 28, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Qiongyang Zhao, Anni Wang
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Publication number: 20230369328Abstract: A semiconductor structure and a method for forming the same are provided.Type: ApplicationFiled: March 29, 2023Publication date: November 16, 2023Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Bo SU, Abraham YOO, Hansu OH, Byung Sup SHIM
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Patent number: 11817355Abstract: A semiconductor device includes a substrate; a gate structure, located over the substrate, the gate structure including a first gate oxide layer, a second gate oxide layer, and a silicon layer. The first gate oxide layer is over the substrate, and the first gate oxide layer has a sloped sidewall on one side and a vertical sidewall on another side. The second gate oxide layer is over the substrate and on the sloped sidewall of the first gate oxide layer, and a thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer. The silicon layer is formed over the first gate oxide layer and the second gate oxide layer.Type: GrantFiled: October 11, 2021Date of Patent: November 14, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Hu Wang, Shan Shan Wang, Feng Qiu, Wei Hu Zhang
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Patent number: 11818874Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.Type: GrantFiled: December 9, 2021Date of Patent: November 14, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Yong Li
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Patent number: 11810787Abstract: A semiconductor structure formation method and a mask are provided.Type: GrantFiled: March 31, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jisong Jin
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Patent number: 11810950Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region; first nanowires formed over the first region of the semiconductor substrate; second nanowires with a diameter smaller than a diameter of the first nanowires formed over the second region of the semiconductor substrate; a first gate layer formed around the first nanowires; and a second gate layer formed around the second nanowires.Type: GrantFiled: September 14, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Huan Yun Zhang, Jian Wu
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Patent number: 11809802Abstract: A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided.Type: GrantFiled: March 11, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Abraham Yoo, Ying Jin, Jisong Jin
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Patent number: 11810903Abstract: A semiconductor structure and a forming method thereof are provided.Type: GrantFiled: March 20, 2023Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jisong Jin
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Patent number: 11810966Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.Type: GrantFiled: March 1, 2022Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Haiyang Zhang, Panpan Liu
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Patent number: 11810860Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.Type: GrantFiled: February 17, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Nan Wang
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Patent number: 11808975Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate, an optical waveguide layer over the base substrate; a first dielectric layer over the base substrate; a cavity between the first dielectric layer and the optical waveguide layer; and a second dielectric layer on the first dielectric layer and the optical waveguide layer. The cavity is located on sidewall surfaces of the optical waveguide layer and has a bottom coplanar with a bottom of the optical waveguide layer. The second dielectric layer is located on a top of the cavity and seals the cavity.Type: GrantFiled: December 27, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Jun Liu, Hong Gang Dai, Dong Xiang Cheng
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Patent number: 11810790Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns.Type: GrantFiled: October 27, 2021Date of Patent: November 7, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Shu Chen
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Publication number: 20230352417Abstract: This disclosure relates to a packaging structure and a packaging method. The packaging structure includes: a substrate; an interconnecting structure, bonded to the substrate, the interconnecting structure is electrically connected to the substrate; a chipset, including a plurality of first chips stacked along a longitudinal direction, the first chip adjacent to the interconnecting structure is used as a bottom chip, each of the rest of the first chips is used as a top chip, the bottom chip is electrically connected to the interconnecting structure, adjacent first chips along the longitudinal direction are electrically connected, and a portion of the bottom chip is exposed from the top chip; a conductive post, arranged on the interconnecting structure on a side of the chipset and electrically connected to the interconnecting structure; and a second chip, bonded to the bottom chip exposed from the top chip and to the conductive post.Type: ApplicationFiled: January 12, 2023Publication date: November 2, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jisong JIN
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Publication number: 20230352468Abstract: This disclosure relates to packaging method and a packaging structure. The packaging structure includes: a substrate, including a bonding surface, a chipset, bonded to the bonding surface and including a plurality of first chips stacked along a longitudinal direction, where the first chip adjacent to the substrate is used as a bottom chip, each of the rest of the first chips is used as a top chip; and a second chip, bonded to the bottom chip exposed from the top chip and to the bonding surface on a side of the chipset, where the second chip, the bottom chip, the top chip, and the substrate are electrically connected, and a projection of the second chip and a projection of the bottom chip on a projection plane parallel to the bonding surface partially overlap. The present disclosure helps improve a speed of communication between chips.Type: ApplicationFiled: January 12, 2023Publication date: November 2, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jisong Jin
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Patent number: 11799018Abstract: A semiconductor structure includes a substrate; and a fin structure disposed on the substrate. The fin structure includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The channel region includes a first nanowire and a second nanowire above the first nanowire. The first nanowire contains first threshold-voltage adjustment ions, and the second nanowire contains second threshold-voltage adjustment ions. A first opening is formed between the first nanowire and the substrate, and between the source region and the drain region, and a second opening is formed between the first nanowire and the second nanowire, and between the source region and the drain region. The first threshold-voltage adjustment ions are different from the second threshold-voltage adjustment ions in type, concentration, or a combination thereof.Type: GrantFiled: August 18, 2020Date of Patent: October 24, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Fei Zhou
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Patent number: 11785755Abstract: A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.Type: GrantFiled: June 23, 2021Date of Patent: October 10, 2023Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventor: Nan Wang
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Patent number: 11784090Abstract: The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.Type: GrantFiled: May 13, 2022Date of Patent: October 10, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Hao Zhang, Xuezhen Jing, Jingjing Tan, Tiantian Zhang, Zhangru Xiao, Zengsheng Xu