Patents Assigned to Semtech Corporation
  • Patent number: 11967610
    Abstract: A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: April 23, 2024
    Assignee: Semtech Corporation
    Inventor: Christopher David Ainsworth
  • Patent number: 11962342
    Abstract: A radio transmitting device configured to transmit a spread-spectrum radio signal wherein a carrier frequency changes in a predetermined set of radio channels according to a hopping sequence, the radio signal being organized in packets having each a header transmitted at a first channel in the hopping sequence comprising a detection sequence, and payload data encoding a message transmitted at following channels in the hopping sequence.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 16, 2024
    Assignee: Semtech Corporation
    Inventors: Olivier Bernard André Seller, Baozhou Ning, Martin Wuthrich
  • Publication number: 20240120912
    Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 11, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Publication number: 20240113920
    Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Publication number: 20240097659
    Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: SEMTECH CORPORATION
    Inventor: Steven Greig PORTER
  • Patent number: 11881476
    Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 23, 2024
    Assignee: Semtech Corporation
    Inventors: Changjun Huang, Jonathan Clark
  • Publication number: 20240021504
    Abstract: A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Applicant: Semtech Corporation
    Inventor: Henry Descalzo Bathan
  • Patent number: 11849387
    Abstract: A methods and apparatuses for supporting device-to-device (D2D) communication in a wireless network is provided. According to embodiments, during a period where a D2D device 1 (D1) and a D2D device 2 (D2) are available for active D2D communications therebetween and when D2 identifies a need for a second communication with at least one of a base station or a different D2D device, the method includes transmitting, by D2, a D2D communication not available message (DNAM) to D1. The DNAM indicates that one or both of D1 and D2 are unavailable for active D2D communications therebetween. Upon receipt of the DNAM by D1, the method further includes transitioning, by D1, to a listening mode for receiving at least a D2D communication available message (DAM) from D2. The DAM indicates that D1 and D2 are available for active D2D communications therebetween.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: December 19, 2023
    Assignee: SEMTECH CORPORATION
    Inventors: Gustav Gerald Vos, Steven John Bennett, Recep Serkan Dost, Nikhil Karande, Lutz Hans-Joachim Lampe
  • Patent number: 11810842
    Abstract: A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 7, 2023
    Assignee: Semtech Corporation
    Inventor: Henry Descalzo Bathan
  • Patent number: 11776951
    Abstract: A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Semtech Corporation
    Inventors: Liping Ren, William Allen Russell
  • Patent number: 11765619
    Abstract: There is provided a method and apparatus for management of internet protocol (IP) flow records in a wireless communication network. The method and apparatus can provide for the compression and aggregation of the IP flow records for subsequent transmission, thereby reducing bandwidth necessary for transmission thereof.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 19, 2023
    Assignee: SEMTECH CORPORATION
    Inventors: Sumit Sourav, Cuero Bugot, Peter John Owens
  • Publication number: 20230275065
    Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 31, 2023
    Applicant: Semtech Corporation
    Inventors: Satyamoorthi Chinnusamy, Kevin Simpson, Mark C. Costello
  • Patent number: 11743022
    Abstract: A method and apparatus for resource allocation for half duplex frequency division duplexing in a wireless communication system is provided. Fixed or variable HARQ timing of greater than 5 subframes may be implemented. Acknowledgements for multiple downlink (uplink) transmissions can be bundled into a single acknowledgement transmitted on an uplink (downlink) control channel. Bundled acknowledgements for downlink transmissions may also be provided. Variable lead time cross subframe scheduling may be provided in which the number of subframes of delay between an uplink or downlink grant and the corresponding scheduled uplink or downlink transmission changes based on other scheduled events and/or half-duplex transceiver availability in the appropriate mode. The scheduling may select the earliest available subframe after a minimum delay. Uplink grant bundling may also be performed, in which multiple uplink grants are transmitted via a single grant indication.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: August 29, 2023
    Assignee: SEMTECH CORPORATION
    Inventor: Gustav Gerald Vos
  • Patent number: 11706819
    Abstract: Methods and apparatuses related to a two-step RACH procedure are provided. Channel conditions can be estimated based on a UE PRACH transmission rather than the subsequent PUSCH transmission in the first part of the two-step RACH. A variable length gap can be provided between the PRACH preamble transmission and the PUSCH transmission. Other solutions are also provided.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: July 18, 2023
    Assignee: SEMTECH CORPORATION
    Inventors: Gustav Gerald Vos, Recep Serkan Dost, Steven John Bennett
  • Patent number: 11698697
    Abstract: A capacitive sensor with a plurality of sense inputs connectable to capacitive sense electrodes and a common reference input, each sense input and the reference input can be put in a measure state, in a ground state, or in a shield state. The sensor can be equipped with external reference capacitors between each of the sense input and the common reference terminal. The reference capacitor can be read individually by selectively pulling one of the input terminals to ground and driving the other to be equipotential with the reference input.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 11, 2023
    Assignee: Semtech Corporation
    Inventors: Chaouki Rouaissia, Pascal Monney
  • Patent number: 11699678
    Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: July 11, 2023
    Assignee: Semtech Corporation
    Inventors: Satyamoorthi Chinnusamy, Kevin Simpson, Mark C. Costello
  • Publication number: 20230197583
    Abstract: A semiconductor device has a substrate and leads formed on two or more sides of the substrate. An electrical component is disposed over the substrate and electrically connected to the lead with bumps or bond wires. The electrical component is encapsulated. A portion of the substrate is removed to form a wettable flank on at least three sides of the lead. The substrate has a molding compound and the lead is disposed within or adjacent to the molding compound. A portion of the molding compound can remain at corners of the substrate. The lead has a first surface or recessed surface on a first side of the lead, a second surface or recessed surface on a second side of the lead, and a third surface or recessed surface on a third side of the lead. A portion of a surface of the lead is plated.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Semtech Corporation
    Inventors: Henry D. Bathan, Yingyu Chen
  • Patent number: 11539605
    Abstract: This application relates to determining transmission quality of a communication channel, in particular for determining a measure of errors in data transmitted as multi-bit symbols. Described is an error checker with an input for receiving an input signal comprising a series of modulated symbols, wherein each symbol encodes multiple bits of a pseudo-random bit sequence. A demodulator is configured to receive the input signal and only partially demodulate at least some of the symbols to generate a partially demodulated bit sequence. A PRBS module is configured to receive the partially demodulated bit sequence and determine the pseudo-random bit sequence and a comparator compares the output of the demodulator to an expected output based on the pseudo-random bit sequence determined by the PRBS module.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: December 27, 2022
    Assignee: SEMTECH CORPORATION
    Inventors: Damien Latremouille, Chad Erven
  • Patent number: 11474648
    Abstract: A mobile device has a proximity sensor. A compensation value of the proximity sensor is determined. The compensation value is compared to a reference compensation value to determine validity of the compensation value. A capacitance of the proximity sensor is measured. A value of the capacitance of the proximity sensor is adjusted based on the compensation value. A coefficient defining a relationship between a capacitance of the proximity sensor and a temperature of the mobile device is calculated. A temperature sensor is coupled to the proximity sensor. The temperature of the mobile device is measured. A value of the capacitance of the proximity sensor is adjusted based on the coefficient and the temperature of the mobile device. The adjusted capacitance value is compared to a threshold capacitance value to determine proximity of an object to the mobile device. A radio frequency signal is adjusted by detecting proximity.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 18, 2022
    Assignee: Semtech Corporation
    Inventors: Chaouki Rouaissia, Jerald G. Ott, III
  • Patent number: 11469149
    Abstract: A semiconductor device has a substrate panel with a substrate having a first substrate area and a second substrate area outside a footprint of the first substrate area. A plurality of semiconductor die or discrete IPDs is disposed over the first substrate area. Substrate area 102a has electrical interconnect for the semiconductor die. A molding compound is disposed over the semiconductor die and first substrate area using a transfer mold process, which leaves mold culls and mold gates disposed over the second substrate area. A substrate edge is formed in the second substrate area under the mold gates. The substrate edge extends into the first substrate area under the molding compound to reinforce the mold gates and reduce cracking during mold degating. The substrate edge can have a variety of forms such as parallel bars, diagonal bars, orthogonal bars, and combinations thereof.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 11, 2022
    Assignee: Semtech Corporation
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho