Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.

Abstract: A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Abstract: A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.

Abstract: A current waveform for an electronic circuit is calculated from a description of the circuit at a given level of abstraction without requiring a detailed simulation. In one embodiment, the waveform is estimated without using test vectors, and uses an analysis time step or “granularity” that is much shorter than a clock cycle. The method is applicable for calculating worst-case instantaneous current.

Abstract: This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that only temporally mutually exclusive currents, or currents whose cumulative sum is less than a predetermined value, can flow in any given switch cell. Techniques for current event merging and current event culling, and techniques for handling timing and current variances may be used.

Abstract: A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an optimal driver for driving the predetermined capacitive load which. simultaneously minimizes the delay and the amount of input capacitance introduced. In one embodiment, a method for selecting a driver for driving a load capacitance from a group of drivers includes: computing for each driver a cost based on a cost function associated with the driver, and selecting the driver having the smallest cost. The cost function is directly proportional to a delay of the driver and inversely proportional to the logarithm of a stage gain of the driver. In another embodiment, the stage gain is an output capacitance driven by the driver (the load capacitance) divided by an input capacitance of the driver.

Abstract: A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.

Abstract: A current waveform for an electronic circuit is calculated from a description of the circuit at a given level of abstraction without requiring a detailed simulation. In one embodiment, the waveform is estimated without using test vectors, and uses an analysis time step or “granularity” that is much shorter than a clock cycle. The method is applicable for calculating worst-case instantaneous current.

Abstract: A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an optimal driver for driving the predetermined capacitive load which simultaneously minimizes the delay and the amount of input capacitance introduced. In one embodiment, a method for selecting a driver for driving a load capacitance from a group of drivers includes: computing for each driver a cost based on a cost function associated with the driver, and selecting the driver having the smallest cost. The cost function is directly proportional to a delay of the driver and inversely proportional to the logarithm of a stage gain of the driver. In another embodiment, the stage gain is an output capacitance driven by the driver (the load capacitance) divided by an input capacitance of the driver.

Abstract: A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.

Abstract: A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.

Abstract: A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserting a delay in a node in an electrical design associated with a logic gate includes: adding the delay at the node by adding a new logic gate before the node where the new logic gate is the same cell type as the logic gate and is positioned near the logic gate. The method may further include: determining if the delay can be added by adding a new logic gate before the node, and if a new logic gate cannot be added before the node, adding the delay by adding a new logic gate after the logic gate where a combination of the logic gate and the new logic gate giving the delay to be added.

Abstract: A method for computing a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver is described. The zero-skew driver insertion point is the position in the area where the spread of the signal arrival times at the nodes driven by the driver is minimized. The method includes: expressing a function describing a distance from each of the nodes to the zero-skew driver insertion point, expressing the variance of the function, minimizing the variance of the function, and solving an equation representative of the minimization of the variance of the function to determine the position of the zero-skew driver insertion point. In one embodiment, the minimizing the variance of the function includes: taking a first derivative of the function with respect to the distance, and setting the first derivative of the function to zero.

Abstract: A clock tree insertion method for distributing a clock signal in an integrated circuit design includes providing a physical design representative of the integrated circuit design, specifying a location for a root node of the clock tree in the physical design, constructing an array of buffers as the clock tree where the array of buffers is constructed to minimize the maximum insertion delay from the root node to the clock signal endpoints and to meet a predefined maximum insertion delay constraint, identifying locations in the clock tree where clock skew violations occur and correcting the clock skew violations by introducing delay at buffer locations in the clock tree having the fastest clock signal arrival times, and identifying locations in the clock tree where minimum insertion delay violations occur and correcting the minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of the clock tree.

Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Abstract: A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.