Patents Assigned to SGS-Thomson Microelectronics
  • Patent number: 7627130
    Abstract: A circuit for processing broadcast signals that includes circuitry for receiving and processing broadcast signals which contain audio information and providing a first audio signal, and circuitry for controlling the amplitude of a received second audio signal in response to a first control signal, and providing a third audio signal wherein the circuit further comprises circuitry that receives the first audio signal and provides the second audio signal for automatically limiting the amplitude of the first audio signal in response to at least one reference signal.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: December 1, 2009
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: Pascal Mellot
  • Patent number: 7149663
    Abstract: A method for selecting an order in which to sift variables in a binary decision diagram. The method includes an act of arranging the variables of the binary decision diagram on nodes of a graph, with the nodes of the graph being labeled with the variables of the system such that a set of functions labeling the leaves reachable from a node correspond to the set of functions which depend on the variables labeling the node. The method further includes an act of traversing the graph in a depth first manner to produce a list of the labels in the selected order.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: December 12, 2006
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: Geoff Barrett
  • Patent number: 7047399
    Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: May 16, 2006
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Andrew C. Sturges, Nathan M. Sidwell
  • Patent number: 7023060
    Abstract: A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region being adjacent to the conduction channel 4, to make it a region with the first type of doping so as to prevent a transistor effect from occurring.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: April 4, 2006
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Pierre Fournel
  • Patent number: 6984872
    Abstract: The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 10, 2006
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Yvon Gris
  • Patent number: 6973056
    Abstract: In transmission systems whereby data packets of a single type and having a fixed structure are used to transmit a given type of information, the invention optimizes the transmission by utilizing data packets of the same type to transmit information of different types and by differentiating the information transmitted in such packets by the rate of re-transmission thereof. In an application of the invention to RDS systems, the block PS is used to transmit both the program service name, as usual, and the radio text, and arrangements are made for the rate of re-transmission of the service name to be high and that of the text to be low, or possibly zero.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: December 6, 2005
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Maurizio Tonella
  • Patent number: 6943592
    Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: September 13, 2005
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Hubert Degoirat, Mathieu Lisart
  • Patent number: 6934202
    Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: August 23, 2005
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Ferrant
  • Patent number: 6914908
    Abstract: The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: July 5, 2005
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Michel Harrand, Claire Henry, Michel Henry
  • Publication number: 20050132141
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Application
    Filed: January 28, 2005
    Publication date: June 16, 2005
    Applicant: STMicroelectronics Limited (formerly SGS-Thomson Microelectronics Limited
    Inventors: Andrew Sturges, David May
  • Patent number: 6885174
    Abstract: The present invention relates to a system for providing a regulated voltage meant to supply a load, including a source for providing a substantially constant current approximately corresponding to the maximum current likely to be surged by the load, and a device receiving the constant current and regulating the load supply voltage, at least one capacitor being connected between an output terminal of the regulation device and the ground.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: April 26, 2005
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean-Michel Ravon
  • Patent number: 6841445
    Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 11, 2005
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Paolo Cappelletti
  • Publication number: 20040173840
    Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 9, 2004
    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
    Inventor: Paolo Cappelletti
  • Patent number: 6781804
    Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: August 24, 2004
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Isabelle Claverie
  • Publication number: 20040095488
    Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well.
    Type: Application
    Filed: July 3, 2003
    Publication date: May 20, 2004
    Applicant: SGS-Thomson Microelectronics, Inc.
    Inventors: Roberto Rambaldi, Marco Tartagni, Alan H. Kramer
  • Patent number: 6710394
    Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: March 23, 2004
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Paolo Cappelletti
  • Publication number: 20040017692
    Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
    Type: Application
    Filed: January 16, 2003
    Publication date: January 29, 2004
    Applicant: SGS-Thomson Microelectronics S.A.
    Inventor: Richard Ferrant
  • Patent number: 6674148
    Abstract: A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the gain or sensitivity of the lateral component, and doping according to the second conductivity type, the back surface, when the gain or the sensitivity of the lateral component is to be increased.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: January 6, 2004
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Eric Bernier, Jean-Michel Simonnet
  • Patent number: 6645803
    Abstract: A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be applied to the fabrication of an adjustable resistor or a MOS transistor having an adjustable threshold.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: November 11, 2003
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Alexander Kalnitsky, Arnaud Lepert
  • Patent number: 6633071
    Abstract: The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal silicide having with the P-type silicon a barrier height lower than or equal to that of the platinum silicide.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: October 14, 2003
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Cyril Furio