Abstract: An electrical power protection integrated circuit provides protection against reverse battery and overvoltage conditions that is particularly of value in automotive applications in which reverse battery and overvoltage conditions are commonplace. The electrical power protection integrated circuit device contains a reverse battery condition protection element, supplied either directly or indirectly from a battery power source, that protects against a reverse battery condition of the battery power source and an overvoltage protection element coupled to the reverse battery condition protection device that protects against an overvoltage condition of the battery power source and produces a protected power output that is isolated from both battery overvoltage and reverse battery voltage conditions. Additionally, the integrated circuit device can further produce an auxiliary protected power output that is isolated from reverse battery voltage conditions.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

Abstract: Methods and apparatuses are provided to identify and extract a torque ripple signal found in the back-emf signal from an electric motor. The torque ripple signal is used in a feedback control loop to reduce the amount and effects of torque ripple in the motor and the motor system. A motor controller is provided to reduce torque ripple in an electric motor. The motor controller is suitable for controlling the speed or torque or other related parameters associated with the electric motor. A disc drive apparatus for use in information storage and retrieval systems is provided. The disc drive apparatus includes an electric motor, an information storage disc, and a motor controller. A method is provided for reducing the effects of torque ripple in an electric motor by sampling the back-emf signal generated by the electric motor, extracting the torque ripple signal from the back-emf signal, and generating an AC component signal proportional to the torque ripple signal.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract: An innovative differential amplifier circuit, which can control the midpoint potential of a load which does not itself have any midpoint connection. This is achieved by using a proxy load element in parallel with the primary load. The proxy load is of much higher impedance value than the primary load, and does have a center tap. The potential of the center tap of the mirrored load is used for a feedback connection to a control loop which regulates the output to both the primary load and the proxy load.

Abstract: A memory access circuit is provided for isolating a matrix memory cell from and coupling a redundant memory cell to a data line when the matrix memory cell is defective. The memory access circuit includes a matrix switch that is coupled between the matrix memory cell and the data line. When the matrix memory cell is defective, a matrix-switch control circuit opens the matrix switch to isolate the defective memory cell from the data line. The memory access circuit also includes a redundant switch that is coupled between the redundant memory cell and the data line. When the defective matrix memory cell is addressed, a redundant-switch control circuit closes the redundant switch to couple the redundant memory cell to the data line in place of the defective memory cell.

Abstract: A restart circuit for an electronic device having a first switch, a second switch, an activation device for initiating a restarting operation of the electronic device when at least one of the first switch and the second switch is in a closed position, and a storage device, capable of being read by the electronic device any time after the restarting operation, for storing in digital format the position of the first switch and the second switch during the initiation of the restarting operation.

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

Abstract: A circuit biases an associated pair of bit lines. A fuse is coupled between a biasing voltage and a node. A first load is coupled between the node and a first of the bit lines. A second load is coupled between the node and a second of the bit lines.

Abstract: A pulse width modulated (PWM) motor drive with back EMF monitoring of the floating phase of a polyphase motor is arranged so that zero crossings of the back EMF can be read without interference by PWM switching. A measure is taken of an interval between two zero crossings and, in the next interval, the PWM switching is stopped near to and before the next expected zero crossing, based on the time of the last prior interval. A period counter counts up during the first interval and another counter, loaded with the previous count reached by the period counter, counts down at the same rate during the second interval until a certain number is reached, near to but before zero, to generate a signal that results in stopping PWM switching until after the next zero crossing is detected.

Abstract: Integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer.

Abstract: A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.

Abstract: A non-linear integrator of a closed loop integration system selectively modifies the gain of the closed loop integration system in order to avoid system saturation while still experiencing high gain in a desired linear portion of the system. A non-linear integrator structure and method allow the gain of the closed loop integration system to be selectively modified in order to avoid saturation while experiencing high gain. The non-linear integrator includes an amplifier, a current source element which generates a bias input signal, a bias circuit which provides the bias input signal to the amplifier and allows the bias input signal to be selectively modified, a storage element coupled to the amplifier, and a gain element, coupled to the storage element, which produces an output signal determined by voltage on the storage element. A voltage input signal and a bias input signal are supplied to the amplifier which generates an amplifier output signal.

Abstract: A zero current enable circuit and zero current enable method are disclosed. The integrated circuit features at least one sense circuit and a logic gate. The sensing circuit combines a broken band gap reference voltage, a voltage divider, a voltage clamp, a comparator, and a logic gate to generate an enable signal.

Abstract: A method for forming sloped contact corners of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first oxide layer is formed over the integrated circuit. An insulating layer is formed over the oxide layer. The oxide and insulating layers are then patterned and etched to form a contact opening to expose a conductive region underlying a portion of the oxide layer. A second oxide layer is formed in the bottom of the contact opening. The insulating layer is then reflowed to form rounded contact corners after which the second oxide layer is removed.

Abstract: A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Abstract: An integrated circuit motor controller having two or more integrated resistor dividers which produce signals to be compared with each other is disclosed. The circuit is designed to substantially reduce the dependency of the comparison on the reverse bias of the junctions between diffused resistors in the integrated resistor dividers and the silicon into which they are diffused.

Abstract: A structure useful during the fabrication of semiconductor integrated circuits. At least one layer is formed over an insulating layer, and an opening formed to an underlying substrate. A conductive layer is formed over the at least one layer, which simultaneously forms a conductive plug in the bottom of the opening. An insulating layer plug is formed over the conductive plug to provide protection while the conductive layer on the at least one layer is removed.

Abstract: A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.