Abstract: A monolithically formed battery charger may be fabricated as an integral part of a multifunctional integrated circuit or as independent monolithically formed integrated circuit. The monolithically formed battery charger includes at least one step-down converter having a given duty ratio coupled to a battery-terminal interface that provides a stepped-down output voltage and current that may be used to charge a rechargeable battery. The step-down converter includes one or more cascaded monolithically-formed synchronous-buck regulators operating at a frequency of at least one megahertz. Each regulator may include a capacitor, inductor, controller, switch, and rectifier. When cascaded, the high-side output node of a preceding synchronous-buck regulator is connected to the switch in a successive synchronous-buck regulator.

Abstract: A system and method for detecting, measuring, and reporting a time derivate of a current signal (di/dt). A sensing element detects current from a load. The sensing element includes an inductor. The inductor is located in series with the load and includes associated parasitic resistance. A differential potential develops across the inductor and the parasitic resistance. The differential potential is amplified and converted to a single-ended value. The single-ended value is then fed to an analog to digital converter that provides an output representative of di/dt.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: A data comparator that operates on an input voltage signal and a reference voltage signal is disclosed. Internally, the comparator includes replicated circuitry to produce differential gain. Each set of replicated circuitry includes two gain stages for high amplification, high sampling rate, and for reducing kickback noise at the input voltage signal and the reference voltage signal. The comparator may further include self-biased CMOS inverters for cancellation of input offset error and a rail-to-rail regenerative output latch. The circuit can also include a comparator bias circuit that can improve the speed of the auto-zero operation.

Abstract: A system and method for detecting, measuring, and reporting a time derivate of a current signal (di/dt) is provided. A sensing element detects current from a load. The sensing element includes an inductor. The inductor is located in series with the load and includes associated parasitic resistance. A differential potential develops across the inductor and the parasitic resistance. The differential potential is amplified and converted to a single-ended value. The single-ended value is then fed to an analog to digital converter that provides an output representative of di/dt.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: A power distribution management apparatus for supplying power to two or more loads includes a power and clock distribution controller capable of determining voltage, current and clock signal frequency targets for the loads. The apparatus also includes two or more power sources responsive to the controller so as to be selectively coupled with the loads to provide the target voltage and current to the loads. The power sources have switching frequencies of at least one megahertz. The apparatus further includes two or more clock signal sources responsive to the controller and coupled with the loads so as to provide clock signals to the loads at the target frequencies.