Patents Assigned to SHANGHAI HUA NEC ELECTRONICS CO., LTD.
  • Patent number: 8907453
    Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 9, 2014
    Assignee: Shanghai Hua Nec Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Xue, Jia Pan, Hao Li, Ying Cai, Xi Chen
  • Publication number: 20130143386
    Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 6, 2013
    Applicant: SHANGHAI HUA NEC ELECTRONICS CO., LTD.
    Inventor: Shanghai Hua Nec Electronics Co., Ltd.
  • Publication number: 20130119384
    Abstract: A parasitic lateral PNP transistor is disclosed, in which, an N-type implanted region formed in each of two adjacent active regions forms a base region; a P-type doped polysilicon pseudo buried layer located under a shallow trench field oxide region between the two active regions serves as an emitter; and a P-type doped polysilicon pseudo buried layer located under each of the shallow trench field oxide regions on the outer side of the active regions serves as a collector region. The transistor has a C-B-E-B-C structure which alters the current path in the base region to a straight line, which can improve the current amplification capacity of the transistor and thus leads to a significant improvement of its current gain and frequency characteristics, and is further capable of reducing the area and increasing current intensity of the transistor. A manufacturing method of the parasitic lateral PNP transistor is also disclosed.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 16, 2013
    Applicant: SHANGHAI HUA NEC ELECTRONICS CO., LTD.
    Inventor: Shanghai Hua Nec Electronics Co., Ltd.