Abstract: The present disclosure provides an optical annealing apparatus and a method for forming a semiconductor structure. The optical annealing apparatus includes: a platform for carrying a wafer; a light source for emitting an annealing light to the wafer; and a mask layer disposed between the platform and the light source, wherein the mask layer has a pattern opening for allowing the annealing light to pass through, and the annealing light passing through the pattern opening is used for annealing a partial area of the wafer. The optical annealing apparatus and the method for forming the semiconductor structure can simplify the formation process of an ion doped region and reduces costs.

Abstract: The present disclosure provides a memory and a method for forming the same. The memory includes: a substrate including a first region, a second region and a third region; a floating gate structure disposed on the second region of the substrate; a first side wall disposed on the floating gate structure; a first gate structure disposed on a side of the floating gate structure, wherein the first gate structure is electrically coupled with the floating gate structure; a dielectric structure disposed on a surface of the first gate structure; a source line structure disposed on a surface of the dielectric structure, wherein the source line structure is also disposed on a surface of the first region; and a word line gate structure disposed on the third region. Therefore, the performance of the memory can be improved.

Abstract: The present disclosure provides a memory structure and a method for forming the same. The memory structure includes: a substrate; a plurality of discrete composite structures disposed on the substrate, wherein a first opening is formed between adjacent composite structures, and each composite structure includes a first conductive structure, a floating gate structure disposed on both sides of the first conductive structure, an erasing gate structure disposed on the floating gate structure, a first isolation structure, a second isolation structure and a third isolation structure disposed on the erasing gate structure; a plurality of mutually independent source doped regions disposed in the substrate, wherein the plurality of source doped regions are in contact with bottom surfaces of the first conductive structure and the floating gate structure; and a word line structure disposed in the first opening. Therefore, the performance and integration of the memory structure can be improved.

Abstract: A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line.

Abstract: The present disclosure discloses a lithography process method for defining sidewall morphology of a lithography pattern, comprising: Step 1: designing a mask, wherein a mask pattern is formed on the mask, the mask pattern being used to define a lithography pattern; the lithography pattern has a sidewall, and a mask side face pattern structure that defines sidewall morphology of the lithography pattern is provided on the mask pattern, the mask side face pattern structure having a structure that enables an exposure light intensity to gradually change; Step 2: coating a to-be-exposed substrate with a photoresist; Step 3: exposing the photoresist by using the mask, and then performing development to form the lithography pattern; and Step 4: performing post-baking. The present disclosure can define the sidewall morphology of a lithography pattern, facilitating formation of a lithography pattern sidewall with an inclined side face.

Abstract: A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.

Abstract: The present application relates to the technical field of memories, in particular to a flash memory programming check circuit, comprising: a memory cell, wherein a bit line is led out from the memory cell, and a pulse sequence signal with a gradually increasing voltage amplitude is applied to the bit line, so that during a high level period of the pulse sequence signal, the memory cell undergoes a program operation, and during a low level period of the pulse sequence signal, the memory cell undergoes a read detection operation; a pulse sequence generation unit used to generate the pulse sequence signal with a gradually increasing voltage amplitude to the bit line; and a reset unit used to control, when a programming control signal starts to be generated, a voltage of the bit line to drop.

Abstract: A method for making a super junction device includes the following steps: step 1: forming a trench gate, in the forming process of the trench gate, a polysilicon gate being used to fill gate trenches and then first flattening being performed and the width of the gate trench at the leading-out position of the gate structure satisfies the requirement of forming contacts; and step 2: forming a super junction, in the forming process of the super junction, a second epitaxial layer being used to fill a super junction trench and then second flattening being performed. The method can realize an all flat process, can conveniently arrange the trench gate process before the forming process of the super junction, can decrease the thermal processes after the formation of the super junction, can save the mask and can decrease the process cost.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate doped with a first ion, a deep trench structure disposed in the substrate, a barrier doped region disposed on a top of the substrate and the deep trench structure, a first epitaxial layer disposed on the barrier doped region, a body region disposed in the first epitaxial layer, a source region disposed in the body region, a gate structure disposed in the first epitaxial layer, and a collector region disposed at a bottom of the substrate. By means of the semiconductor structure, performance of an insulated gate bipolar transistor can be improved.

Abstract: A high-voltage isolation semiconductor device and a method for manufacturing the same. The method includes providing a first conductivity type substrate of a substrate layer; performing first conductivity type ion implantation by means of first implantation energy to form a first conductivity type buried layer part A; performing first conductivity type ion implantation by means of second implantation energy to form a first conductivity type buried layer part B primary structure, wherein the first implantation energy is greater than the second implantation energy; growing a second conductivity type epitaxial layer on the first conductivity type substrate, wherein the first conductivity type buried layer part B primary structure extends into the second conductivity type epitaxial layer to form a first conductivity type buried layer part B; and forming a first conductivity type well region by means of first conductivity type ion implantation.

Abstract: The present disclosure provides a memory and a method for forming the memory. The memory includes: a substrate including a first storage area and a second storage area; a source region disposed in the substrate between the first storage area and the second storage area; a first drain region and a second drain region in the substrate on both sides of the first storage area and the second storage area; a first storage structure disposed on the first storage area, including a first storage unit, a second storage unit, and a first word line gate; and a second storage structure disposed on the second storage area, including a third storage unit, a fourth storage unit, and a second word line gate. The memory can obtain an improved performance.

Abstract: An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

Abstract: The present application discloses an OPC model simulation method. The method includes the following steps: step 1, establishing a precision judgment function which is formed by multiplying each square of the difference between a simulation point of an OPC model and an actual point on a wafer, by weight, and then superposing all the squares; step 2, performing random data sampling, comprising forming distributed computing nodes; randomly distributing data to each computing node, and meanwhile distributing a current state value of fitting parameter space composed of all fitting parameters to each computing node; computing a local precision judgment function of each computing node; step 3, performing parallel computing to obtain the gradient of each local precision judgment function, and computing a first derivative and a first order approximate value of the gradient of each local precision judgment function; step 4, performing gradient composition and iteration.

Abstract: A method for manufacturing an IGBT device includes: forming a source of the IGBT device in a substrate, wherein the substrate is an MCZ substrate; performing annealing processing on the substrate, wherein a layer of oxide is formed on the surface of the source during an annealing process; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is comprised of a silicon nitride layer, a first type oxide layer, and a second type oxide layer, and a material used to form the first type oxide layer is different from a material used to form the second type oxide layer; and performing nitrogen annealing processing on the substrate.

Abstract: The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

Abstract: A photolithographic exposure method for a memory. In a photolithographic process for making a memory, when exposure is performed by using a mask, regions with different exposure dimension requirements on the memory are divided into different exposure groups. Regions with the same exposure resolution requirement are divided into the same group. Different exposure modes of exposure that are capable of correspondingly satisfying resolution requirements of each group are performed to different groups during exposure. During exposure, different illumination modes are adopted to perform exposure. Firstly, a first exposure mode is adopted to perform exposure to a memory array cell exposure group, then a wafer is kept stationary on a supporting platform, and then a second exposure mode is adopted to perform exposure to the other structure exposure group; after the exposure of all groups is completed, one-step development is performed to complete pattern transfer.

Abstract: A switching LDMOS device is formed first well in a semiconductor substrate that includes an LDD region and a first body doped region; a first heavily doped region serving as a source region is provided in the LDD region, and a second heavily doped region serving as a drain region is provided in the first body doped region; a channel of the switching LDMOS device is formed at a surface layer of the semiconductor substrate between the LDD region and the body doped region and below the gate structure; and one side of the LDD region and one side of the body doped region which are away from the gate structure both are provided with a field oxide or STI, and one side of the field oxide or STI is in contact with the first heavily doped region or the second heavily doped region.

Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.

Abstract: A shield gate trench power device, wherein a shield dielectric layer is formed by stacking a thermal oxide layer and a CVD dielectric layer on the inner side surface of a gate trench; a gap region formed by means of filling with the shield dielectric layer is filled with source polysilicon; a top trench is formed on two sides of the source polysilicon by etching a portion of the shield dielectric layer close to the side surface of the gate trench, and the entire top trench is located in the thermal oxide layer; the top trench is filled with a polysilicon gate. A method for manufacturing a shield gate trench power device. The uniformity of the thickness of the shield dielectric layer on the sidewall and bottom of the gate trench can be improved.

Abstract: A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.