Abstract: The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench, a gate conductive material layer formed on the surface of the gate dielectric layer, and a second dielectric layer filling a second trench formed between a second side face of a drain shallow trench isolation and a first side face of the first trench. The depths of the first trench and the second trench are equal. The first trench and the second trench connect with each other to form an overall trench. Bottom surfaces of the second dielectric layer and the gate dielectric layer are flush with each other. A first side face of the gate conductive material layer extends to the surface of the second dielectric layer. The present application also discloses a method for manufacturing the HV device.

Abstract: The present application discloses a method for manufacturing a metal zero layer, comprising: step 1, etching a zero interlayer film to form a first trench; step 2, performing first Ge ion implantation to form a first Ge layer in the zero interlayer film and achieve first amorphization; step 3, performing second Ge ion implantation to form a second Ge layer in the zero interlayer film and achieve second amorphization, wherein the depth of the second Ge layer is greater than the depth of the first Ge layer, and the second Ge ion implantation is tilt ion implantation; step 4, forming a metal silicide layer on the surface of an amorphous silicon layer in a self-aligned manner; step 5, filling the first trench with a first metal layer; and step 6, performing chemical mechanical polishing to fully remove the first metal layer outside the first trench and achieve planarization.

Abstract: The present application discloses a method for manufacturing a metal gate, comprising: step 1, providing a semiconductor substrate on which dummy polysilicon gates are formed, wherein a first gate dielectric layer is formed at the bottom of the dummy polysilicon gates, and a spacing region between the dummy polysilicon gates is filled with a zero interlayer dielectric; step 2, removing the dummy polysilicon gates, comprising: step 21, performing first dry etching to remove a part of the thickness of the dummy polysilicon gate; step 22, performing carbon ion implantation to form a carbon containing surface region of the zero interlayer dielectric; and step 23, performing second wet etching to fully remove the remaining dummy polysilicon gates; step 3, performing third etching to remove the first gate dielectric layer; and step 4, forming a second gate dielectric layer and a metal gate.

Abstract: The present application relates to a wafer transfer module in a semiconductor manufacturing machine, relating to semiconductor integrated circuit manufacturing machines, wherein two sets of transmitter/receivers are provide on sidewalls of the wafer transfer module to monitor the travel position of an elevator, two sets of transmitter/receivers are provide on the sidewalls of the wafer transfer module to monitor the position of a transfer arm, a signal received by the receiver is transmitted to a control system such that the control system determines, according to the travel position of the elevator and the transfer arm position, whether the transfer arm can obtain a to-be-transferred wafer, thereby preventing the problem of a wafer scratch caused by an elevator position deviation or a transfer arm position deviation.

Abstract: The present application provides a method for monitoring a gate oxide thickness: providing a device structure comprising a gate structure, a gate oxide layer under the gate structure, source and drain regions and a base region; applying a voltage ?Vdd on the gate structure so that an accumulation layer is formed between the source and drain regions, applying a small AC voltage on the basis of the gate voltage ?Vdd; grounding the source and drain regions; applying a voltage signal close to 0 potential on the base region; obtaining the capacitance Cox between the gate structure and the base region by testing; and obtaining the thickness of a gate oxide layer according to the formula Tox=?*S/Cox. This technique accurately monitors the thickness of the gate oxide layer, and avoids those errors caused by existing methods.

Abstract: The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.

Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Abstract: The present application provides a method for reducing a loss of a dielectric layer in an IO silicon oxide removal process, a plurality of gate structures arranged on a silicon bulk and spaced apart from each other, and an IO silicon oxide layer located between the bottom of the gate structure and the silicon bulk; depositing an etch stop layer; the gate structure being composed of a polysilicon structure, a first hard mask layer, and a second hard mask layer stacked from bottom to top; depositing a first dielectric layer to fill a space between the gate structures; performing etch back of the first dielectric layer; depositing a silicon nitride layer to continuously cover an upper surface of the first dielectric layer and an upper surface of the exposed etch stop layer; depositing a second dielectric layer on the silicon nitride layer.

Abstract: The present application provides a method for forming a SiGe channel, FDSOI structure comprising a silicon substrate, a first silicon oxide layer and a silicon layer, wherein the silicon layer is covered with a hard mask layer, a groove region that penetrates through upper and lower surfaces of the hard mask layer is formed on the hard mask layer, and the groove region exposes an upper surface of the silicon layer; forming a SiGe film in the groove region; forming a second silicon oxide layer on an upper surface of the SiGe film; removing the hard mask layer; and performing a thermal treatment on the stack structure in an atmosphere of ammonia and oxygen to form a SiO2-SiGe channel. According to the present application, the SiGe channel is formed to reduce a relaxation risk of SiGe during a subsequent thermal treatment process.

Abstract: The present application provides a method for improving a copper alloy electroplating filling process, forming a groove on a semiconductor structure; forming a barrier layer on the surface of the groove, and then covering the barrier layer with a seed layer; electroplating the seed layer in the groove with copper, until an upper surface of the copper in the groove is close to an opening of the groove; adding impurity metal ions into an electroplating solution for copper electroplating to continue the electroplating, wherein during an electroplating process, the impurity metal ions are fully consumed quickly, forming an alloy layer on the surface of the copper; continuing the copper electroplating on the alloy layer in the groove; repeating steps 4 and 5 until the groove is fully filled; and performing chemical mechanical polishing, the polishing ending at the opening of the groove.

Abstract: The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

Abstract: The present application discloses a wet clean apparatus for a single wafer, comprising: a baffle arranged on the periphery of the wafer bearing platform. The anti-splash structure comprises: a first vertical plate, wherein a length direction thereof is perpendicular to the surface of the wafer; a first opening transversely passing through the first vertical plate, wherein the first opening is arranged on a movement track of the etchant shaken off from the surface of the wafer; and a second transverse plate, wherein a first end thereof is fixedly arranged on the outer side surface of the first vertical plate, the top surface of the second transverse plate is horizontal and is lower than or flush with the bottom surface of the first opening, and the etchant passing through the first opening flows on the top surface of the second transverse plate and is decelerated.

Abstract: The application discloses a super flash including: a first gate trench formed at the top of a source region, wherein a floating gate and a control gate are formed in the first gate trench. A second nitrogen oxide layer and a first oxide layer are formed between a first side surface of the floating gate and side and bottom surfaces of the first gate trench. A third nitrogen oxide layer and a fourth oxide layer are formed between a second side surface of the floating gate and a side surface of the control gate. The floating gate is a TiN layer; and the top of the floating gate is higher than a top surface of the control gate. The second nitrogen oxide layer and the third nitrogen oxide layer prevent the diffusion of oxygen into the floating gate. The present application also discloses a method for manufacturing a super flash.

Abstract: The present application discloses a capacitor integrated in a FinFET. The capacitor and a resistor are both integrated in a middle-end-of-line process layer. A resistor main body layer and a resistor cover layer of the resistor and the forming regions of the intermediate dielectric layer and the lower electrode plate of the capacitor are patterned in a lithography process applying a first photomask; a forming region of an upper electrode plate is patterned in another lithography process applying a second photomask; the lower electrode plate, the upper electrode plate and the resistor main body layer are respectively connected with a metal zeroth layer. The present application further discloses a method for fabricating a capacitor integrated in a FinFET device. The disclosed method can reduce the process cost and improve the process efficiency, as well as flexibly select the capacitance of the capacitor by the process.

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: The present application discloses a design for testability circuit of an SRAM. In a write path circuit detection mode of a fault diagnosis logic control module, a write path circuit is in an on state, a write data bit multiplexer is in a selected state, a read data bit multiplexer is in a deselected state, a read path circuit is in an on state, and a memory cell is in a selected state; in a read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, and the memory cell is in a deselected state. A bit line signal end is connected to a test signal outputted by a signal generation circuit.

Abstract: The present application provides a distributed LDO regulator structure without an external capacitor. The structure includes one CORE module; and one or more POWER modules driven by one of the CORE modules. The CORE module comprises a mirror source voltage generating circuit and a built-in LDO regulator circuit. An output end of an operational amplifier and a gate of the sixth PMOS together serve as a control voltage end of the POWER module. A negative input end of the operational amplifier is connected to a drain of the fifth PMOS and a source of the sixth PMOS by means of a first resistor, wherein a connection end serves as an output end of the built-in LDO regulator circuit. POWER modules having the same output voltage are connected to each other in parallel.

Abstract: A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate.

Abstract: The application discloses a method for manufacturing a metal zero layer, comprising: step 1, providing a semiconductor substrate that undergoes a source and drain formation process of FEOL, wherein an inter-gate trench is formed in an area between dummy gate structures; step 2, forming a cut-off layer of metal zero layer in a selected area of the inter-gate trench; step 3, forming a metal zero layer in the inter-gate trench outside the cut-off layer of metal zero layer, and etching back the metal zero layer; step 4, forming a second oxide layer, the second oxide layer fully filling the inter-gate trench on the top surface of the metal zero layer, performing a planarization process to make the top surface of the second oxide layer level with the top surface of the dummy gate structure; and step 5, removing the dummy gate structure, and forming a second gate structure.

Abstract: The present application provides a reaction device for improving epitaxial growth uniformity, provided with a main inject port on one side and an exhaust port on the other side, wherein a base is provided between the main inject port and the exhaust port; the reaction cavity is provided with first and second inject pipes; the length directions of the first and second inject pipes are perpendicular to a connecting line between the main inject port and the exhaust port; the lengths of the first and second inject pipes are both equal to the radius of the base; the first and second inject pipes are located in a straight line along the length directions; the first and second inject pipes are each provided with a plurality of holes; and the plurality of holes on the first and second inject pipes are located above the wafer placed on the base.