Abstract: A liquid crystal display device includes a TFT array substrate (first substrate), a counter substrate (second substrate), a liquid crystal layer, and a common electrode (first electrode), an insulating film, and pixel electrodes 21 (second electrode) that are provided on the TFT array substrate. Each of the pixel electrodes 21 has a plurality of linear electrodes 26 and a first connection portion 27. Each of the linear electrodes 26 has a main line portion 29 and a first bent portion 30. An additional capacitance portion 32 is provided integrally with the first connection portion 27 in a region along an arrangement direction of a plurality of first bent portions 30.

Abstract: First and second vapor deposition particles (91a, 91b) discharged from first and second vapor deposition source openings (61a, 61b) pass through first and second limiting openings (82a, 82b) of a limiting plate unit (80), pass through mask opening (71) of a vapor deposition mask (70) and adhere to a substrate (10) so as to form a coating film. If regions on the substrate to which the first vapor deposition particles and the second vapor deposition particles adhere if the vapor deposition mask is assumed not to exist are respectively denoted by a first region (92a) and a second region (92b), the limiting plate unit limits the directionalities of the first vapor deposition particles and the second vapor deposition particles in a first direction (10a) that travel to the substrate such that the second region is contained within the first region. Accordingly, it is possible to form a light emitting layer with a doping method by using vapor deposition by color.

Abstract: The present invention is intended to provide a parallel data-processing device comprising a plurality of ring-like interconnected processors, which is capable of conducting high-speed calculations with a plurality of matrices and neural nets. A data processing device according to the present invention comprises a plurality of interconnected unit processors each of which comprises a first data-holding means and storage means consisting of a second data-holding means and connecting means. The connecting means of each processor has inputs, outputs and a state variable. Input and output connections of the connecting means change depending upon a state of the state variable.