Abstract: A method is provided for promoting adhesion of CVD copper to diffusion barrier material in integrated circuit manufacturing. The method includes depositing a first seed layer of copper on the barrier material by chemical vapor deposition (CVD) using (hfac)Cu(1,5-Dimethylcyclooctadiene) precursor. Following the deposition of the seed layer, which strongly adheres and conforms to the copper receiving surfaces on the diffusion barrier, the wafer substrate is positioned in an electro-chemical deposition apparatus, such as an electroplating or electroless plating bath. A second layer of copper is then deposited on the seed layer by means of electrochemical deposition, e.g., electroplating or electroless plating. The second layer of copper deposited by electro-chemical deposition is a “fill” or “bulk” layer, substantially thicker than the seed layer.

Abstract: The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes.

Abstract: A method for etching a metallic surface on an integrated circuit (IC) is provided to minimize electrical resistance between the metallic surface and subsequently applied chemical vapor deposition (CVD) copper. The metallic surface is etched with the ions of an inert gas, such as Ar, at low energy levels. A low energy level minimizes the penetration of ions into the metallic surface, and the use of an inert gas minimizes chemical interactions between the metallic surface and the ions. CVD copper is then applied to the etched surface. In one embodiment, an inert gas and oxygen ions are used to prepare the metallic surface. The inert gas ions are used to etch the metallic surface to improve conductivity, and the oxygen ions promote the formation of an oxide layer to improve adhesion between the metallic surface and the copper. An IC comprising a copper stud to interconnect dielectric interlevels with improved electrical conductivity is also provided.

Abstract: An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

Abstract: A method has been provided for improving the adhesion of Cu to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The diffusion barrier is exposed to either a reactive oxygen species, or a plasma containing oxygen. A thin layer of the diffusion barrier is oxidized, typically less than 50 .ANG., in response to exposure to the oxygen environment. CVD copper is then deposited over the oxidized diffusion barrier surface. The oxide layer improves bonding between the copper and diffusion barrier surfaces. The oxide layer permits the control of tolerances in the diffusion barrier preparation processes, and copper precursor, to be relaxed. An integrated circuit comprising an oxide layer between the diffusion barrier and the copper layer is also provided.

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Abstract: A method has been provided for improving the adhesion of Cu to a diffusion barrier material, such as TiN, in an integrated circuit substrate. The diffusion barrier material is exposed to either a reactive gas species, or a plasma containing a reactive gas. By removing contaminants on the surface of the diffusion barrier, and forming weak molecular bonds between the diffusion barrier surface and the reactive gas, the diffusion barrier surface is protected and prepared for Cu adhesion. Cu, breaking the bonds between the reactive gas and diffusion barrier surface, readily bonds to the diffusion material for improved adhesion between surfaces. The diffusion barrier surface, prepared with the reactive gas, allows the IC to be stored, delaying the Cu deposition to more convenient times in the IC fabrication process. An Cu conductor interface adhered to the diffusion barrier of an integrated circuit is also provided.

Abstract: A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.

Abstract: A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.

Abstract: A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level.

Abstract: The invention provides a process for depositing fluorinated amorphous carbon (a-F:C) films on IC wafers to provide a low-k interconnect dielectric material. The process, carried out in a PECVD chamber, introduces silane gas (SiH.sub.4) into the mixture of C.sub.4 F.sub.8 and CH.sub.4 gases used to deposit a-F:C films. The silane helps to decrease the fluorine etchants in the deposited film, helping to improve the crosslinks in the deposited product. Film produced in accordance with the present invention has both low-k, generally below 2.4, and high thermal stability, generally above 440.degree. C., allowing for higher thermal anneal temperatures.

Abstract: A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.

Abstract: A polarizer film tool, for removal of polarizer film from an LCD panel, is provided. The tool includes a take-up cylinder whose rotational action pulls the film from the LCD and wraps the removed film around itself. Two padded rotating stabilization cylinders guide the LCD in a preferred path through the tool to equally distribute the force used to hold the LCD as the polarizer film is pulled from its surface. The padded cylinders allow for deviations in the preferred path to accommodate any discrete parts mounted on the LCD that have a higher profile than the LCD surface. A method for removing the polarizer film with the above-mentioned tool is also provided.

Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.

Abstract: A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is provided. The method prepares both the metal and non-metallic surfaces with a low energy ion etch of an inert gas through the use of an ion gun. The etching promotes the growth of copper on the metallic surface, and inhibits the growth on the non-metallic surface. Following an application of CVD copper, the surfaces are etched again to clean any residual copper from the non-metallic surface, and to again prepare the surfaces for another deposition of copper. Through repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness, while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures.

Abstract: A cellular telephone transmitter is provided, including a selectable gain microphone amplifier, to transmit vocal signals to the receiver of a communicating telephone. The telephone transmitter including a variable gain amplifier to amplify the vocal signal picked up by the microphone, a gain controller to vary the gain of the amplifier, and a selector associated with the gain controller which allows the telephone user to choose the gain of the amplifier. The telephone user intermittently activates the selector, while speaking, to choose an amplifier gain level appropriate to the volume of the input vocal signal. In particular, the user can elect to temporarily boost the gain while whispering into the phone. A method is also disclosed.

Abstract: A digital signal processor on an integrated circuit uses a multi-port data flow structure characterized by four ports, referred to as an acquisition port, two data ports, and a coefficient port. All four ports may be bidirectional so that data may be read from and written to the respective ports by the DSP system. This architecture allows a data flow management scheme in which data enters the processor through the acquisition port, or any one of the data ports. As the data is processed, it may ping pong between the data ports, or between a data port and the acquisition port. At the end of a DSP algorithm, the output data may be provided through the acquisition port or a data port as suits the needs of the particular application. A coefficient port is typically used for providing coefficients or twiddle factors for DSP algorithms. A DSP system is provided which includes a digital signal processor having four ports as discussed above. Each data port is attached to dedicated, independent data memory.

Abstract: A method is provided for a mobile station to calculate the time intervals at which it monitors cells in a cellular phone system to find the mobile station's home network in the phone system. The monitoring varies with the rate at which the mobile station reselects proximate cells to locate itself in a telephone network. The time between cell selections is used as an indication of the mobile station's mobility. The variable search intervals, determined by the time intervals at which the mobile station reselects cells, is limited to insure that the mobile station at least monitors for its home network at a minimum specified interval of time. An apparatus is also provided to initiate home network monitoring at time intervals related to rate at which cells in a cellular phone system are reselected by a mobile station.

Abstract: A system and method has been provided to selectively deliver a plurality of trigger signals to a counter/timer embedded in a microprocessor. The method provides the step of selecting a signal, from either internal or external sources, to trigger the counter/timer. If an internal source is selected, the method provides the step of selecting either a synchronous or non-synchronous signal source to trigger the counter/timer. Regardless of the source chosen, the method includes the step of generating a signal output from the selected source, and the further step of delivering the trigger signal on a dedicated connection. The method of the present invention also includes the step of counting clock cycles in response to the arrival of the trigger signal to the counter/timer. An apparatus to selectively deliver a trigger signal to a counter/timer embedded in a microprocessor from a plurality of signal sources is also provided.

Abstract: A method is provided for forming silicided source/drain electrodes in active devices wherein the electrodes have very thin junction regions. In the process silicidation material is deposited on the wafer and rapid-thermal-annealed at a temperature and for a time calculated to produce metal-rich or silicon-deficient silicide on the electrodes. The metal-rich or silicon-deficient silicide is selectively formed on the semiconductor electrodes and not on oxide or other insulating surfaces. A selective etch removes the silicidation material which has not reacted with silicon, including metal overlying insulating surfaces. Then, after cleaning the silicide surfaces, a layer of silicon is deposited over the structure and a second rapid thermal anneal is performed at a higher temperature than the first rapid thermal anneal.