Abstract: A liquid-cooled plate radiator is disclosed. The liquid-cooled plate radiator includes a radiator body. A coolant liquid runner for circulating a coolant liquid is formed inside the radiator body. The coolant liquid runner includes a plurality of radiating sub-runners. Then, a plurality of fin units are arranged on the radiating sub-runners along a flow direction of the coolant liquid. The fin unit has a plurality of fins extending side by side along the flow direction of the coolant liquid. Moreover, the fins of the front and rear adjacent fin units on the radiating sub-runners are staggered, thereby increasing the radiating area, enhancing the disturbance of the coolant liquid when flowing inside the radiating sub-runners, and improving the radiating efficiency. Thus, the technical problems of limited radiating area and low radiating efficiency caused by a single linear coolant liquid runner are solved.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Abstract: A test circuit (300, 300?, 400, 500, 600, 700, 800), including: a test sequence providing module (301), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (303); a clock driving module (307, 407, 507, 607, 707, 807), configured to provide a clock signal (759) to the to-be-tested sequential device (303), which includes a first clock driving circuit (610, 710), wherein the first clock driving circuit (610, 710) includes: a plurality of first clock paths (421, 423) which respectively provide corresponding clock signals (759); and a logic unit (427, 715) which generates, based on at least part of the clock signals (759) provided by the plurality of first clock paths (421, 423), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (303); and a verification module (305, 405, 805), configured to verify an output of the to-be-tested sequential device (303).

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present application relates to a supercomputing server including: a case housing defining an accommodating space and provided with a mounting hole allowing communication between the accommodating space and an external environment; and a control unit disposed at an end portion of the case housing corresponding to the mounting hole and configured to be moved into or out of the accommodating space through the mounting hole. After the control unit is disassembled from the case housing, the control unit may be moved out of the accommodating space through the mounting hole at the end portion of the case housing to maintain the control unit. After the maintenance, the control unit is moved into the accommodating space through the mounting hole, and the control unit is fixed at the end portion of the case housing.

Abstract: The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, configured to receive input data; an output terminal, configured to provide output data in response to the input data; clock signal terminal(s), configured to receive clock signal(s); a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s); and a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s), where the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal, and where the output terminal is configured to use data from the second latch unit as the output data for outputting.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: The present application discloses a rotary liquid distributor for a liquid-cooled tank, and a liquid-cooled tank. The rotary liquid distributor includes a liquid distribution cavity and a liquid distribution arm provided in the liquid distribution cavity. The liquid distribution cavity rotates around a central shaft thereof. A plurality of the liquid distribution arms are uniformly distributed in a circumferential direction of the liquid distribution cavity. That is, the liquid distribution arm rotates with the liquid distribution cavity. Then, a liquid distribution outlet is provided between a first end and a second end of the liquid distribution arm. The liquid distribution outlet is located on a side of the liquid distribution arm facing away from a rotating direction.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: Disclosed in embodiments of the present application are a liquid-cooling heat dissipation apparatus, a liquid-cooling data processing device and a temperature equalization method. The liquid-cooling heat dissipation apparatus includes a housing unit and a first liquid-cooling plate arranged in the housing unit. A first electronic unit and a second electronic unit are arranged on a first cooling surface and a second cooling surface arranged oppositely of the first liquid-cooling plate respectively, and the first electronic unit and the second electronic unit may be, for example, hashboards, that is, in the liquid-cooling heat dissipation apparatus provided in the embodiment of the present application, one liquid-cooling plate is correspondingly provided with two hashboards.

Abstract: A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.

Abstract: Implementations of the present application propose a method and apparatus for preventing rollback of firmware of a data processing device, and a data processing device. The method includes: enabling a boot loader (BootLoader) to read a current value of a predetermined bit in a one-time programmable memory (eFuse); determining whether the current value and a legal value written into the one-time programmable memory after the latest updating of the firmware of the data processing device satisfy a preset relationship; in response to determining that the current value and the legal value satisfy the preset relationship, enabling the boot loader to call an operating system kernel of the data processing device, and in response to determining that the current value and the legal value do not satisfy the preset relationship, enabling the boot loader not to call the operating system kernel of the data processing device.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: A liquid-cooled plate radiator is disclosed. The liquid-cooled plate radiator includes a radiator body. A coolant liquid runner for circulating a coolant liquid is formed inside the radiator body. The coolant liquid runner includes a plurality of radiating sub-runners. Then, a plurality of fin units are arranged on the radiating sub-runners along a flow direction of the coolant liquid. The fin unit has a plurality of fins extending side by side along the flow direction of the coolant liquid. Moreover, the fins of the front and rear adjacent fin units on the radiating sub-runners are staggered, thereby increasing the radiating area, enhancing the disturbance of the coolant liquid when flowing inside the radiating sub-runners, and improving the radiating efficiency. Thus, the technical problems of limited radiating area and low radiating efficiency caused by a single linear coolant liquid runner are solved.

Abstract: An operational circuit of a virtual currency data processing device includes: at least two operational chip groups configured to operate within respective operating voltage threshold ranges of the operational chip groups to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal; a control module configured to operate within an operating voltage threshold range to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups to make the operational chip groups and the control module capable of identifying communication signals sent by each

Abstract: A control circuit of a large data processing device system for virtual currency and a large data processing device for virtual currency using the control circuit. The control circuit includes: at least two co-controllers (12), each of the co-controllers (12) being in communication connection with one hashboard group (14), to communicate with the connected hashboard group (14) and control operation of the connected hashboard group (14); and a main controller (11) in communication connection with each of the co-controllers (12), to receive and submit tasks and perform, according to the received tasks, coordinated control and task allocation on each of the co-controllers (12), each of the hashboard groups (14) including at least one hashboard.

Abstract: Disclosed are a liquid cooling plate suitable for liquid cooling heat dissipation of an electronic device and a heat dissipation unit. The liquid cooling plate includes a liquid cooling plate body and at least one heat dissipation flow channel, wherein the liquid cooling plate body is provided with a first heat dissipation surface and a second heat dissipation surface that are arranged in parallel, the first heat dissipation surface being planar, a plurality of heat dissipation bosses being arranged on the second heat dissipation surface, and heat dissipation flow channels extending along the heat dissipation bosses are provided inside the liquid cooling plate body at positions corresponding to the at least one of the heat dissipation bosses between the first heat dissipation surface and the second heat dissipation surface, the plurality of heat dissipation flow channels being connected to form a cooling liquid flow path having an inlet and an outlet.