Abstract: A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.

Abstract: A novel and useful apparatus and method for an image-interferer aware single quadrature RF downconversion (SQRD) low intermediate frequency (LIF) receiver and related power reduction techniques utilized therein. The invention applies zero-margin adaptive transceiver (ZMAT) design principles to considerably reduce the receiver's power consumption in an adaptive fashion in accordance with the instantaneous reception conditions. In a low IF dual-branch (i.e. quadrature) downconversion receiver, the radio monitors the image strength and shuts off the receiver's Q branch (or I branch) when image rejection is not needed (i.e. when the relative image strength is below a threshold), thus significantly reducing power consumption in the RF receiver. A zero IF receiver is switched to a SQRD low IF receiver of lower power consumption when the image interferer strength is low enough to allow for a given required level of performance.

Abstract: A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.

Abstract: A novel and useful apparatus and method for an image-interferer aware single quadrature RF downconversion (SQRD) low intermediate frequency (LIF) receiver and related power reduction techniques utilized therein. The invention applies zero-margin adaptive transceiver (ZMAT) design principles to considerably reduce the receiver's power consumption in an adaptive fashion in accordance with the instantaneous reception conditions. In a low IF dual-branch (i.e. quadrature) downconversion receiver, the radio monitors the image strength and shuts off the receiver's Q branch (or I branch) when image rejection is not needed (i.e. when the relative image strength is below a threshold), thus significantly reducing power consumption in the RF receiver. A zero IF receiver is switched to a SQRD low IF receiver of lower power consumption when the image interferer strength is low enough to allow for a given required level of performance.

Abstract: A novel and useful apparatus and method for an image-interferer aware single quadrature RF downconversion (SQRD) low intermediate frequency (LIF) receiver and related power reduction techniques utilized therein. The invention applies zero-margin adaptive transceiver (ZMAT) design principles to considerably reduce the receiver's power consumption in an adaptive fashion in accordance with the instantaneous reception conditions. In a low IF dual-branch (i.e. quadrature) downconversion receiver, the radio monitors the image strength and shuts off the receiver's Q branch (or I branch) when image rejection is not needed (i.e. when the relative image strength is below a threshold), thus significantly reducing power consumption in the RF receiver. A zero IF receiver is switched to a SQRD low IF receiver of lower power consumption when the image interferer strength is low enough to allow for a given required level of performance.

Abstract: A novel and useful apparatus and method for an image-interferer aware single quadrature RF downconversion (SQRD) low intermediate frequency (LIF) receiver and related power reduction techniques utilized therein. The invention applies zero-margin adaptive transceiver (ZMAT) design principles to considerably reduce the receiver's power consumption in an adaptive fashion in accordance with the instantaneous reception conditions. In a low IF dual-branch (i.e. quadrature) downconversion receiver, the radio monitors the image strength and shuts off the receiver's Q branch (or I branch) when image rejection is not needed (i.e. when the relative image strength is below a threshold), thus significantly reducing power consumption in the RF receiver. A zero IF receiver is switched to a SQRD low IF receiver of lower power consumption when the image interferer strength is low enough to allow for a given required level of performance.

Abstract: A novel and useful adaptive antenna tuner and associated calibration mechanism for passive adaptive antenna matching networks. The tuner is suitable for use with cellular antennas and in one embodiment uses MEMS based tunable devices. The tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates one or more update control signals for the tuning algorithm which drives the MEMS-based tunable devices.

Abstract: A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract: A novel and useful RF oscillator suitable for use in applications requiring ultra-low voltage and power. The oscillator structure, employing alternating current source transistors, combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The oscillator can be incorporated within a wide range of circuit applications, including for example a conventional phase locked loop (PLL), all-digital phase-locked loop (ADPLL), wireline transceiver circuits and mobile devices.

Abstract: A novel and useful 60 GHz frequency generator based on a third harmonic extraction technique which improves system level efficiency and performance. The frequency generator employs a third harmonic boosting technique to increase the third harmonic at the output of the oscillator. The oscillator generates both ˜20 GHz fundamental and a significant amount of the third harmonic at ˜60 GHz and avoids the need for a frequency divider operating at 60 GHz. The undesired fundamental harmonic at ˜20 GHz is rejected by the good fundamental harmonic rejection ratio (HRR) inherent in the oscillator buffer stage while the ˜60 GHz component is amplified to the output. The fundamental harmonic is further suppressed by active cancellation by properly combining the two outputs. The oscillator fabricated in 40 nm CMOS exhibits a phase noise of ?100 dBc/Hz at 1 MHz offset from a 60 GHz carrier and have a tuning range of 25%.

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.