Abstract: A synchronization circuit for video clock generators, wherein in order to obtain a line synchronization simultaneous with a complete image synchronization, there is provided a follow-up control which delivers a clock frequency signal. The follow-up control has its reference input connected with the output of a line pulse-separation circuit, delivering an external horizontal pulse signal, and is further connected with the input of an external complete image characteristic or marker pulse-separation circuit. Both of the separation circuits have infed at their input side a mixed pulse signal. The external complete image-characteristic pulse-separation circuit is connected at its output side with the first input of a comparator, the second input of which has infed thereto the output signal of an internal complete image characteristic pulse-separation circuit.