Abstract: A split video architecture in accordance with the present invention merges or composites the video data into a common frame buffer with the desktop data. For example, pixels of a first format (e.g., RGB) can be sent directly to the monitor. Pixels of a second format (e.g., YUV) can be filtered and color space converted from the second format to the first format (e.g., YUV to RGB) in the backend, and then the converted values can be sent to the monitor. To accommodate such operation, exemplary embodiments are configured to inform the backend which pixels are of the first format (e.g., RGB) and which are of the second format (e.g., YUV).

Abstract: A novel circuit is provided which allows a storage register to load data from another register utilizing a store signal which is asynchronous to the clock signal used to store data in the first register. A novel store circuit is provided which provides a control signal in response to a store signal, which conditionally loads data into the storage register. The contents of the storage register is either maintained or overwritten, depending upon the relationship of the store signal to the clock signal.

Abstract: A programmable frequency synthesizer includes a first memory (e.g., ROM) for storing a plurality of pre-programmed frequencies, a second memory (e.g., RAM) for storing at least one user input programmable frequency, and dual purpose frequency synthesizer inputs for providing command address information to select one of the pre-programmed frequencies from the first memory and for providing serial data representing a user input programmable frequency to be stored in the second memory. The frequency synthesizer further includes a control input and decoder for directing the address information and the user input programmable frequency data to the first or second memory, respectively.

Abstract: An all-MOS voltage to current converter is provided in which the resistor of a conventional voltage to current converter is replaced by one or more transistors. The transistors are all subject to the same process variations, solving the tracking problem that can occur using both analog and digital components. An output current is produced as a linear function of an input voltage using first and second MOSFETs by impressing a first voltage related to the input voltage across the first MOSFET transistor and, while operating the first MOSFET in its linear region, producing a first current through the first MOSFET having a magnitude related to the first voltage. The first voltage is then level-shifted by a predetermined voltage to produce a level-shifted voltage. The level-shifted voltage is applied to the second MOSFET, which is operated in its saturated region, producing a second current through the second MOSFET having a magnitude related to the level-shifted voltage.

Abstract: Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance.

Abstract: A method of performing anti-aliasing on polynomial curves using only integer arithmetic. The anti-aliasing method includes the steps of: defining an polynomial equation of a curve, dividing grid units into an finite number of sub-intervals, associating a mix ratio to each of the sub-intervals, determining which sub-interval the curve bisects, assigning a mix ratio to each picture element bordering the grid unit according to the mix ratio associated with the sub-interval determined to be bisected by the curve.

Abstract: An efficient data storage scheme for an echo canceller for a high-speed modem provides for storing in bulk memory, instead of a trellis-encoded codewords, unencoded words of lesser length in bits. For a v.32terbo modem operating at 19,200 bps, for example, the unencoded word has only eight bits as compared to nine bits for the trellis-encoded codeword. Therefore, one memory word (16 bits) can be used to store two unencoded words, resulting in memory savings of 50%. More particularly, in accordance with one embodiment of the invention, full-duplex, high-speed data communications using echo cancellation is performed by storing in memory transmit data represented in a first form, at predetermined intervals substantially equal to a round-trip delay time, reading out transmit data from memory and trellis-encoding the transmit data to produce trellis-encoded transmit data, and performing echo cancellation using data derived from the trellis-encoded transmit data.

Abstract: A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range.

Abstract: A data transfer mechanism is provided between a host device and a slave device in which the slave bus width is automatically configured according to mode information, and the exact number of slave cycles required are generated according to the host request. In particular, a bus interface controller interfaces a host device having a host bus of a predetermined physical bus width to a slave device having a slave bus of a variable one of multiple possible logical bus widths, where the host device physical bus width in bits is an integer multiple of the slave device logical bus width in bits. First circuitry is responsive to a request from the host device for exchanging handshaking signals with the slave device to execute a number of slave bus transfer cycles until a last cycle signal has been received, and for returning a completion signal to the host device.

Abstract: A telephone system includes a data modem that is coupled to a control microprocessor and a Data Access Arrangement (DAA) for detecting a Caller ID. The detected information is used to select a specific action dependent upon the specific Caller ID. Only one relay is needed with no other parts to connect the Caller ID to the data modem. A programmed Intelligent Work Station (IWS) determines whether to respond to the call and the type of response.

Abstract: A virtual sensing system includes a sensing network that is external to a standard cell for sensing a reference current in the standard cell and for generating a scaled current without breaking the reference current path and without inserting any sensing device in series with the reference current. The reference current can be used, for example, for duplication and/or scaling.

Abstract: An apparatus for generating a substantially constant voltage control signal using either one of a voltage reference source and a current reference source includes a transistor device responsive to a supply voltage and the voltage control signal to produce a controlled current, an operational amplifier device for generating the voltage control signal in response to the voltage reference source, and a switching device for generating the voltage control signal in response to the current reference source. When the switching device is in one state thereof, an output signal of the operational amplifier device is connected through the transistor device in a closed loop back to an input terminal of the operational amplifier device. When the switching device is in another state thereof, the output signal of the operational amplifier device is connected directly in the closed loop back to an input terminal of the operational amplifier device.

Abstract: Echo attenuation facilitates achievement of efficient, full-duplex data communications on two-wire channels. Major advantages are achieved by using an adaptive hybrid in conjunction with echo cancellation. When needed, the adaptive hybrid reduces the amplitude range requirements on the echo canceller and on analog-to-digital conversion, thereby reducing overall cost. This reduction in range requirements reduces the digital word-size required for high-performance echo cancellation and reduces the bit-accuracy needed in the analog-to-digital converter. These reductions in needed word-size and bit accuracy substantially reduce implementation cost. Normally, the adaptive hybrid is used to reduce near-end echoes, which are usually much larger than far-end echoes. The echo canceller attenuates the remaining near-end echo and the far-end echo. Two major objectives are: (1) Cost effectiveness and (2) versatile, effective correction of echoes with various, realistic characteristics.

Abstract: A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.

Abstract: In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.