Abstract: An integrated circuit and a configuration method thereof are disclosed. The integrated circuit, applied to a neural network model calculation, includes a first operator engine, a second operator engine, a random access memory (RAM) and a direct memory access (DMA) engine. The first operator engine is configured to perform a first calculation operation. The second operator engine is configured to perform a second calculation operation. The DMA engine performs an access operation on the RAM according to a first memory management unit (MMU) table when the first operator engine performs the first calculation operation, and performs an access operation on the RAM according to a second MMU table when the second operator engine performs the second calculation operation.

Abstract: An output circuit includes a comparator circuit, a voltage conversion circuit and a signal output circuit. The comparator circuit detects an operating mode based on a first supply voltage and a second supply voltage and generates a first control signal. The voltage conversion circuit adjusts a level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts a level of a digital signal according to the first voltage, the second voltage and the first supply voltage to generate a digital output signal corresponding to the operating mode.

Abstract: The present invention discloses a wireless network detection apparatus. A storage circuit stores virtual wireless communication apparatus information. A wireless signal transmission circuit communicates using a wireless communication protocol. A processing circuit executes software or firmware executable commands to perform a wireless network detection method including the steps outlined below. Whether a wireless signal including non-predetermined electronic apparatus identification information being received is determined. When the wireless signal is received, an existence signal is broadcasted accordingly. A first-time pairing information that is transmitted from a non-predetermined electronic apparatus based on the existence signal is received to perform the first-time pairing and store the non-predetermined electronic apparatus identification information in the storage circuit.

Abstract: A convolution calculation apparatus applied for convolution calculation of a convolution layer includes a decompression circuit, a data combination circuit and a calculation circuit. The decompression circuit decompresses compressed weighting data of a convolution kernel of the convolution layer to generate decompressed weighting data. The data combination circuit combines the decompressed weighting data and non-compressed data of the convolution kernel to restore a data order of weighting data of the convolution kernel. The calculation circuit performs calculation according to the weighting data of the convolution kernel and input data of the convolution layer.

Abstract: An image correction method and a processor are disclosed. The method includes performing a feature point search on a quick response (QR) code image to determine multiple feature points, dividing a coded area of the QR code image into multiple sub-regions according to the multiple feature points, determining a compensation vector for each sub-region according to the feature points corresponding to each sub-region, and compensating and correcting each sub-region according to the compensation vector of each sub-region to obtain a corrected image. Thus, the solution provided by the present application can avoid interference between different sub-regions by means of correcting the QR code image in a regional manner using the compensation vectors, thereby more accurately correcting the distortion of the QR code image.

Abstract: A line driver includes a first resistive component, a second resistive component, an operational amplifier and an adjustable current mirror array circuit. A first terminal of the second resistive component and the first resistive component are coupled to a node, and a second terminal of the second resistive component is coupled to an output terminal. The operational amplifier receives a common mode voltage through the first resistive component, and generates a first signal and a second signal according to the common mode voltage and an input signal. The adjustable current mirror array circuit generates a first current to the node and a second current to the output terminal in response to the first and second signals, and adjusts a ratio of the second current to the first current in response to multiple control bits so as to set an output impedance of the output terminal.

Abstract: A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a validation signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the validation signal. The first starting voltage is lower than the second starting voltage.

Abstract: An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiply-add circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.

Abstract: A control circuit and a control method of an image sensor are provided. The image sensor generates a sensed data. The control circuit includes a statistical circuit, an auto exposure (AE) circuit, and a calculation circuit. The statistical circuit generates a luminance statistical data according to the sensed data. The AE circuit sets the image sensor and outputs an AE data which includes a target luminance of the image sensor. The calculation circuit controls an operation mode of the image sensor according to the luminance statistical data and the AE data.

Abstract: A memory device includes first memory circuits and first memory controller. The first memory controller is configured to receive a first command from a first circuitry. When the first memory controller controls a first circuit in the first memory circuits to operate in an enable mode in response to the first command, the first memory controller is further configured to control remaining circuits in the first memory circuits to operate in a data retention mode in response to the first command.

Abstract: A clock generator device includes a detector circuit, a calibration circuit, and a free running oscillator. The detector circuit is configured to determine whether a reference clock signal is received from a transmission interface to output an enable signal. The calibration circuit is configured to generate a first signal in response to the enable signal and an output clock signal, and compare the first signal with a predetermined value to generate a calibration signal. The free running oscillator is configured to adjust a frequency of the output clock signal in response to the calibration signal.

Abstract: An method, a computer readable medium and a system for an automated design of a controllable oscillator are provided, wherein the method includes: receiving a set of input data through an automated design procedure, wherein the set of input data includes an initial circuit description file and a criteria file, and the initial circuit description file records initial values of parameters of one or more components within the controllable oscillator; performing simulation according to the set of input data through the automated design procedure to generate a simulation result; and selectively modifying at least one parameter within the parameters of the one or more components according to the simulation result through the automated design procedure. In addition, in the process of modifying the at least one parameter, connection relationships of all components within the controllable oscillator are unchanged.

Abstract: The present disclosure discloses an object detection method used in an object detection apparatus that includes the steps outlined below. An image signal received from an image sensor is detected to generate an image detection signal when an image variation is detected. An infrared signal received from an infrared sensor is detected to generate an infrared detection signal when an infrared energy variation is detected. A time counting process is initialized when the image detection signal is generated. An object detection signal is generated when the infrared detection signal is generated within a predetermined time period after the time counting process is initialized. A detection distance of the image sensor is larger than a detection distance of the infrared sensor.

Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.

Abstract: A frequency divider circuit is provided. The frequency divider circuit processes multiple input clocks. The frequency divider circuit includes a frequency dividing circuit and a retiming circuit. The frequency dividing circuit generates an intermediate clock according to a first subgroup of the input clocks. The retiming circuit generates multiple output clocks according to a second subgroup of the input clocks and the intermediate clock. The periods of the input clocks are all a first period, and the periods of the output clocks are all a second period. The first period is smaller than the second period. The frequency dividing circuit and the retiming circuit operate according to a mode control signal which determines a ratio of the first period to the second period.

Abstract: A virtual memory management method applied to an intelligent processor including an operation accelerator includes: determining m storage units from a physical memory, the m storage units forming a virtual memory; dividing the m storage units into n storage groups; determining an address mapping relationship for each storage group to obtain n address mapping relationships, the n address mapping relationship being correspondence of between n virtual addresses of the virtual memory and physical addresses of the m storage units, where m and n are dynamically updated according to requirements of the operation accelerator. In the method, the number of the storage units in each storage group can be configured according to requirements of the operation accelerator, and a data storage bit width and a data storage depth of the virtual memory are dynamically updated to thereby improve data access efficiency.

Abstract: A data temporary storage apparatus includes a moving unit coupled to a first storage unit and multiple second storage units. The moving unit receives a moving instruction having contents including a read address, a destination address and a predetermined moving rule. The moving unit further executes the moving instruction to fetch input data by row from the first storage unit according to the read address, and to temporarily stores one after another in an alternate and sequential manner the data in each row to each of the second storage units indicated by the destination address. The data moving, data reading and convolution approaches of the present invention implement in parallel data moving and a convolution operation, achieving a ping-pong operation of convolution units and enhancing convolution efficiency, while reducing memory costs since configuring two data storage spaces in a memory is not necessary.

Abstract: A control method for a storage device of a driving recorder includes: configuring a directory entry of a storage device according to a predetermined directory entry stored in a storage unit; configuring a file allocation table of the storage device according to a predetermined file allocation table stored in the storage unit; and controlling a controller to write data to the storage device according to the directory entry and the file allocation table. In one embodiment, entries of the predetermined file allocation table are interleaved to accommodate multiple files and still support a continuous write operation.

Abstract: A method for preventing image modification, an image capturing device and an image verification method are disclosed. The image modification method includes: processing a compressed image of at least one frame to obtain feature data of the compressed image of the at least one frame; encrypting the feature data to generate a checksum; generating supplemental enhancement information, which at least includes a time parameter and the checksum; and transmitting and/or storing the supplemental enhancement information and the compressed image of the at least one frame together so as to verify authenticity of the compressed image of the at least one frame by using the supplemental enhancement information. The time parameter is a counter value of a counter in the image capturing device and the counter value continuously increases. With the above method, authenticity of image data can be verified.

Abstract: The present disclosure discloses a face identification system that includes an image-retrieving circuit, an invisible light source and a processing circuit. The image-retrieving circuit includes light-sensing elements each including a plurality of visible light sensors and an invisible light sensor. The processing circuit executes software and firmware executable commands to execute a face identification method that includes the steps outlined below. An invisible light is emitted to an object to be identified by the invisible light source. A visible light sensed frame and an invisible light sensed frame are retrieved by using the visible and invisible light sensors. Determine whether a light reflection related parameter of the invisible light sensed frame is within a predetermined range is determined only according to the invisible light sensed frame. When the light reflection related parameter is within the predetermined range, the object to be identified is determined to be a real face.