Abstract: An optical sensing device can include: a semiconductor having a photosensitive region; an optical structure located above the photosensitive region; and where the optical structure comprises alternately stacked light-filtering layers and light-transmitting layers, in order to block large-angle incident light from entering the photosensitive region.

Abstract: A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is in contact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type.

Abstract: A metal-oxide-semiconductor device can include: a base layer; a source region extending from an upper surface of the base layer to internal portion of the base layer and having a first doping type; a gate structure located on the upper surface of the base layer and at least exposing the source region, and a semiconductor layer located on the upper surface of the base layer and having the first doping type, where the semiconductor layer is used as a partial withstand voltage region of the device, and the source region is located at a first side of the gate structure, the semiconductor layer is located at a second side of the gate structure, and the first side and the second side of the gate structure are opposite to each other.

Abstract: A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.

Abstract: A method of controlling a multi-phase power converter having a plurality of power stage circuits coupled in parallel, can include: obtaining a load current of the multi-phase power converter; enabling corresponding power stage circuits to operate in accordance with the load current, such that a switching frequency is maintained within a predetermined range when the load current changes; and controlling the power stage circuits to operate under different modes in accordance with the load current, such that the switching frequency is maintained within the predetermined range when the load current changes.

Abstract: A package device can include: a package body having a support body and an encapsulating body configured to encapsulate a conductive body of the package device; at least one extraction electrode electrically connected to the conductive body, and having a part exposed outside the package body; and where the support body is located on only part of a bottom surface of the encapsulating body, and protrudes from the bottom surface of the encapsulating body to form a cavity defined by the remaining exposed bottom surface of the encapsulating body and inner side surface of the supporting body.

Abstract: A method of controlling a power convertor to perform diming control for a light-emitting diode (LED) load, can include: adjusting a length of a switching period of the power converter in accordance with a dimming signal; and controlling the power converter to generate a drive current corresponding to the dimming signal.

Abstract: A driving circuit and a driving method are provided. The driving circuit includes a power stage circuit and a full-bridge circuit. The power stage circuit is configured to receive an input voltage, and generate an output voltage at an output port of the power stage circuit. The full-bridge circuit is coupled to the output port of the power stage circuit and is configured to perform charging and discharging on a piezoelectric load. An operating mode of the full-bridge circuit is controlled, so that a supply voltage signal for driving the piezoelectric load during a first operating interval of an operating cycle corresponds to a reference voltage in a first interval, and the supply voltage signal during a second operating interval of the operating cycle corresponds to the reference voltage in a second interval. The driving circuit has a small volume, which is conducive to circuit integration.

Abstract: A method of manufacturing a semiconductor device can include: forming an interlayer dielectric layer on an upper surface of a lower metal layer, the lower metal layer including first and second regions; forming a through hole extending from an upper surface of interlayer dielectric layer to the lower metal layer to expose the upper surface of the lower metal layer; forming a conductive layer covering a bottom part and sidewall parts of the through hole, and the upper surface of the interlayer dielectric layer; forming a first dielectric layer covering the first conductive layer on the first region of the lower metal layer; filling the through hole with a first metal; and forming an upper metal layer above the upper surface of the interlayer dielectric layer.

Abstract: A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to generate an encoded signal according to the input digital signal; an isolation element having a primary winding, a first secondary winding, and a second secondary winding; a differential circuit configured to receive first and second differential signals, and to generate a difference signal according to the first and second differential signals; and a decoding circuit coupled with the differential circuit, and being configured to receive the difference signal, and to generate a target digital signal after decoding.

Abstract: A driving circuit and a driving method are provided. According to embodiments of the present disclosure, a power switch is driven by constant voltage or constant current during different time periods. The power switch is driven by using a first driving current during a Miller platform period, and the power switch is driven by using a second driving current when the Miller platform period ends, where the first driving current is less than the second driving current, so as to optimize EMI, reduce loss and improve efficiency.

Abstract: An apparatus includes a plurality of control modules coupled to a multi-phase power converter having a plurality of power stage circuits correspondingly coupled to the plurality of control modules, where each control module includes: a first port coupled to a second port of a previous control module; a second port coupled to a first port of a next control module, and being configured to generate a transmission signal for the next control module; and where the transmission signal represents at least two types of information, and is configured to control the corresponding power stage circuit to operate sequentially.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: A power converter can include: positive and negative input terminals configured to receive an input voltage; positive and negative output terminals configured to generate an output voltage; first and second power switches sequentially coupled in series between the positive input terminal and a first node; third and fourth power switches sequentially coupled in series between a second node and the negative input terminal, where there is no physical connection between the first node and the second node; a first energy storage element coupled between a common terminal of the first and second power switches and a common terminal of the third and fourth power switches; a first multi-level power conversion circuit coupled between the first node and the positive output terminal; and a second multi-level power conversion circuit coupled between the first node and the positive output terminal.

Abstract: A control circuit for a resonant converter, that is configured to: adjust a conduction time of one power switch and a conduction time of one corresponding synchronous rectifier switch in the resonant converter in a resonant period detection mode; control a resonance current to cross zero twice during the conduction time of the synchronous rectifier switch; and obtain a resonant period of the resonant converter.

Abstract: An integrated driver applied to a voltage converter having a switched capacitor conversion circuit, the integrated driver including: a first die having a first-type power transistor; a second die including at least one second-type power transistor, where a withstand voltage of the first-type power transistor is higher than a withstand voltage of the second-type power transistor; and where the first die and the second die are coupled in series between a high potential terminal and a low potential terminal of the voltage converter, such that the first-type power transistor receives a high voltage signal.

Abstract: A power converter can include: N switching power stage circuits, where output terminals of the N switching power stage circuits are connected in parallel, and N is a positive integer; an energy storage element coupled between an input terminal and the output terminal of the power converter, where the energy storage element is configured to periodically store energy for delivery to the output terminal of the power converter; and where after a main transistor of an M-th switching power stage circuit is turned off, a main transistor of the (M+1)-th switching power stage circuit is turned on, in order to realize zero-voltage-switching (ZVS) of the main transistor of (M+1)-th switching power stage circuit, where M is a positive integer less than N.

Abstract: A switching power supply circuit can include: an energy storage capacitor; a high-frequency switching network coupled to the energy storage capacitor, and being configured to receive a low-frequency AC input voltage, to charge the energy storage capacitor, to perform high-frequency chopping on the low-frequency AC input voltage and/or a voltage of the energy storage capacitor, and to generate a high-frequency AC signal; and a rectifier module coupled to the high-frequency switching network, and being configured to receive the high-frequency AC signal, to rectify the high-frequency AC signal, and to generate a DC signal.

Abstract: A power converter can include at least one first power stage circuit and a second power stage circuit, where each of the at least one first power stage circuit can include: at least one power switch, configured as a main power switch; a first magnetic element; a first energy storage element configured to be coupled to a first node of the first power stage circuit together with one adjacent power stage circuit, and to be charged or discharged through the adjacent power stage circuit; and an auxiliary module configured to ensure that a current flowing through the first magnetic element is not less than zero in a current discontinuous mode, where a first terminal of the second power stage circuit is coupled to an adjacent first power stage circuit.

Abstract: A method of controlling a switching converter having a plurality of interleaved parallel branches, can include controlling conduction phases of power switches of the plurality of interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter. A control circuit for a switching converter with a plurality of interleaved parallel branches, can control conduction phases of power switches of the interleaved parallel branches to be overlapped when a load changes from a light load to a heavy load, in order to improve dynamic response performance of the switching converter.