Abstract: A display is capable of displaying images in response to signals of a plurality of signal formats. The display includes a controller that is coupled to a plurality of image data interfaces. When the plurality of image data interfaces are simultaneously operating, the controller selects one of the plurality of image data interfaces according to preference variables associated with each of the plurality of image data interfaces. Each of the preference variables may indicate a relative priority of an image data signal format associated with the corresponding image data interface. In addition, each of the preference variables may indicate one or more performance metrics associated with the quality of image data signals received from the corresponding image data interface.

Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.

Abstract: Methods and apparatus for maintaining and utilizing system memory defect tables that store information identifying defective memory locations in memory modules. For some embodiments, the defect tables may be utilized to identify and re-map defective memory locations to non-defective replacement (spare) memory locations as an alternative to replacing an entire memory module. For some embodiments, some portion of the overall capacity of the memory module may be allocated for such replacement.

Abstract: The system includes a chassis and a printed circuit board (e.g., a motherboard) that is attached to the chassis. The system further includes an actuator that is slidably engaged with the chassis and a cam plate that is rotatably engaged with the chassis. The actuator engages the cam plate such that maneuvering the actuator rotates the cam plate. The system further includes a blade (e.g., an electronic module) which is slidably engaged with the chassis such that the blade slides in a first direction within the chassis as the blade is inserted into the chassis. The blade is inserted into the chassis until the blade engages the cam plate. The cam plate engages the blade such that rotation of the cam plate causes the blade to continue to move in the first direction and engage the printed circuit board.

Abstract: A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

Abstract: A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input configurations, such as by moving a digitizing stylus on the sensing grid formed on the dome enclosure surface. This interaction affects the content of the volumetric display by mapping positions and corresponding vectors of the stylus to a moving cursor within the 3D display space of the volumetric display that is offset from a tip of the stylus along the vector.

Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).

Abstract: Mapping of cacheable memory pages from other processes in a parallel job provides a very efficient mechanism for inter-process communication. A trivial address computation can then be used to look up a virtual address that allows the use of cacheable loads and stores to directly access or update the memory of other processes in the job for communication purposes. When an interconnection network permits the cacheable access of one host's memory from another host in the cluster, kernel and library software can map memory from processes on other hosts, in addition to the memory on the same host. This mapping can be done at the start of a parallel job using a system library interface. A function in an application programming interface provides a user-level, fast lookup of a virtual address that references data regions residing on all of the processes in a parallel job running across multiple hosts.

Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

Abstract: A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.

Abstract: A system and method of reducing back flow in an air mover having one or more blades is described. A flap is attached to a blade of the air mover such that, when back flow occurs, the flap obscures all or a portion of the space between blades during back flow.

Abstract: A system and method for rendering with an object proxy. In one embodiment, a method includes forming a set of view textures corresponding to a set of viewing directions; selecting a viewing direction for rendering; selecting at least two view textures from the formed set based on the selected viewing direction; and rendering the object proxy at the selected viewing direction. The rendering step includes applying texture from the selected view textures onto the selected object proxy. The view texture set forming step includes: calculating texture coordinates for the object proxy based on the level of obstruction at different portions of the object proxy and texture packing data; and drawing portions of the object based on the level of obstruction data for the object proxy and based on the texture packing data to obtain a view texture at the selected viewing direction.

Abstract: A method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video. Spatial compositing uses a graphics unit or pipeline to render a portion (subarea) of each overall frame of digital video images. This reduces the amount of data that each processor must act on and increases the rate at which an overall frame is rendered. Optimization of spatial compositing depends on balancing the processing load among the different pipelines. The processing load typically is a direct function of the size of a given subarea and a function of the rendering complexity for objects within this subarea. Load balancing strives to measure these variables and adjust, from frame to frame, the number, sizes, and positions of the subareas. The cost of this approach is the necessity to communicate, in conjunction with each frame, the graphics data that will be rendered. Graphics data for a frame is composed of geometry chunks.

Abstract: A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.

Abstract: A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries. A queuing circuit having a plurality of registers interconnected by 2:1 multiplexers is also provided. The circuit is arranged such that each register receives either its own current contents or the contents of a higher order register during each register write cycle.

Abstract: A compact flat panel color calibration system includes a lens prism optic able to pass a narrow, perpendicular, and uniform cone angle of incoming light to a spectrally non-selective photodetector. The calibration system also includes a microprocessor operable to determine the luminance of the display based upon the information gathered by the photodetector. A software module included in the calibration system is then operable to process the luminance information in order to adjust the flat panel display.

Abstract: The present invention provides a method and system for presenting three-dimensional computer graphics images using multiple graphics processing units. The dimensions of the scene to be rendered are bounded by a rectangular volume decomposed into rectangular subvolumes. Vertices of graphics primitives are compared with subvolume boundaries to determine to which subvolume a graphics primitive should be assigned. A GPU is assigned to each subvolume to render the graphics data that lies within it. A viewing position point is determined and communicated to each GPU. Rendered graphics data from each GPU are ordered based upon the viewing position Outputs of the individual GPUs are combined by blending within an image combiners. Outputs of image combiners can be presented for viewing or further combined in a subsequent stage image combiner.

Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.