Patents Assigned to Silicon Graphics International Corp.
  • Patent number: 9686206
    Abstract: The present invention relates to a temporal base method of mutual exclusion control of a shared resource. The invention will usually be implemented by a plurality of host computers sharing a shared resource where each host computer will read a reservation memory that is associated with the shared resource. Typically a first host computer will perform and initial read of the reservation memory and when the reservation memory indicates that the shared resource is available, the first host computer will write to the reservation memory. After a time delay, the host computer will read the reservation memory again to determine whether it has won access to the resource. The first host computer may determine that it has won access to the shared resource by checking that data in the reservation memory includes an identifier corresponding to the first host computer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 20, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventors: Joseph Carl Nemeth, Kevan Flint Rehm
  • Patent number: 9665923
    Abstract: A system, method, and computer program product are provided for remote rendering of computer graphics. The system includes a graphics application program resident at a remote server. The graphics application is invoked by a user or process located at a client. The invoked graphics application proceeds to issue graphics instructions. The graphics instructions are received by a remote rendering control system. Given that the client and server differ with respect to graphics context and image processing capability, the remote rendering control system modifies the graphics instructions in order to accommodate these differences. The modified graphics instructions are sent to graphics rendering resources, which produce one or more rendered images. Data representing the rendered images is written to one or more frame buffers. The remote rendering control system then reads this image data from the frame buffers. The image data is transmitted to the client for display or processing.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 30, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Phillip C. Keslin
  • Patent number: 9654142
    Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 16, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
  • Patent number: 9632934
    Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 25, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Brian J. Johnson
  • Patent number: 9619288
    Abstract: A system for deploying big data software in a multi-instance node. The optimal CPU memory and core configuration for a single instance database is determined. After determining an optimal core-memory ratio for a single instance execution, the software is deployed in multi-instance mode on single machine by applying the optimal core-memory ratio for each of the instances. The multi-instance database may then be deployed and data may be loaded in parallel for the instances.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: April 11, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: Sanhita Sarkar, Raymon Morcos
  • Patent number: 9619180
    Abstract: The present system enables more efficient I/O processing by providing a mechanism for maintaining data within the locality of reference. One or more accelerator modules may be implemented within a solid state storage device (SSD). The accelerator modules form a caching storage tier that can receive, store and reproduce data. The one or more accelerator modules may place data into the SSD or hard disk drives based on parameters associated with the data.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 11, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Kirill Malkin
  • Patent number: 9612745
    Abstract: Embodiments of the presently claimed invention enable a RAID set to appear as if it were initialized immediately after a command to initialize a RAID set is initiated. Typically, a driver or other software in the software stack intercepts the command to initialize the RAID set. The driver then responds to user application programs as if the RAID set initialization is complete, even when it is not. After intercepting the RAID set initialization command, the driver will intercept and respond to data read or write commands as if the RAID set were initialized. The driver or other software will then, typically initialize the RAID set using background tasks. In certain instances, data stored in a non-RAID configuration may be migrated to a RAID configuration during the initialization process.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Larry Fenske
  • Patent number: 9613035
    Abstract: A primary data storage system is connected with a separate and external active archive storage system to consolidate data and allow active archive data to be managed based on primary storage system events. The primary data storage system may be managed and maintained by an external entity, and may include a manager module such as a resource manager. The active archive system may include several tiers of storage in a hierarchical storage system and logic for moving data between and among the tiers. As data processing milestones are completed or the state of data changes, in projects stored in the primary data storage system, task milestone or state change events are detected. Event detection can trigger data movement in the active archive solution. One or more software modules implementing the present invention may detect the events and trigger active archive operations based on the events.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventor: Floyd William Christofferson
  • Patent number: 9612920
    Abstract: Data state rollover is performed based on data state snapshots and deltas. A series of snapshots is taken of the current data state, an original data state, and data states in between. Deltas are then generated between two sequential snapshots. This results in numerous deltas which represent the difference between consecutive snapshots. Once the deltas are acquired, the deltas may be stored along with the snapshot of the present data state. As such, previous data states may be rolled back to by determining the number of deltas to apply to the current data state to achieve the desired previous data state. In cases where the rollback or rollover fails, deltas may be played against the current data state to a point where the last known trusted and working data point existed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 4, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: John Michael Sygulla, Arun Ramakrishnan, Greg Slowiak
  • Patent number: 9606588
    Abstract: A cooling system for a high performance computing system includes a closed-loop cooling cell having two compute racks and a cooling tower between the compute racks. Each compute rack includes at least one blade enclosure, and the cooling tower includes at least one water-cooled heat exchanger and one or more blowers configured to draw warm air from a side of the compute racks towards a back, across the water-cooled heat exchanger, and to circulate cooled air to a side of the compute racks towards a front. The cooling cell further includes a housing enclosing the compute racks and the cooling tower to provide a closed-loop air flow within the cooling cell. The cooling system further includes cooling plate(s) configured to be disposed between two computing boards within the computing blade, and a fluid connection coupled to the cooling plate and in fluid communication with the blade enclosure.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 28, 2017
    Assignee: Silicon Graphics International Corp.
    Inventors: Steven J. Dean, David R. Collins, Timothy Scott McCann, Perry D. Franz, Jeffrey M. Glanzman
  • Patent number: 9606874
    Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 28, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventors: Daniel Moore, Andrew Gildfind
  • Patent number: 9547882
    Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 17, 2017
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Cheng Liao
  • Patent number: 9519657
    Abstract: A computer system with read/write access to storage devices creates a snapshot of a data volume at a point in time while continuing to accept access requests to the mirrored data volume by copying before making changes to the base data volume. Multiple snapshots may be made of the same data volume at different points in time. Only data that is not stored in a previous snapshot volume or in the base data volume are stored in the most recent snapshot volume.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: December 13, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Kenneth S. Beck
  • Patent number: 9514092
    Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: December 6, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Martin M. Deneroff, Gregory M. Thorson, Randal S. Passint
  • Patent number: 9513844
    Abstract: The present system enables more efficient I/O processing by providing a mechanism for maintaining data within the locality of reference. One or more accelerator modules may be implemented within a solid state storage device (SSD). The accelerator modules form a caching storage tier that can receive, store and reproduce data. The one or more accelerator modules may place data into the SSD or hard disk drives based on parameters associated with the data.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 6, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Kirill Malkin
  • Patent number: 9513934
    Abstract: A system deploys visualization tools, business analytics software, and big data software in a multi-instance mode on a large, coherent shared memory many-core computing system. The single machine solution provides or high performance and scalability and may be implemented remotely as a large capacity server (i.e., in the cloud) or locally to a user. Most big data software running in a single instance mode has limitations in scalability when running on a many-core and large coherent shared memory system. A configuration and deployment technique using a multi-instance approach, which also includes visualization tools and business analytics software, maximizes system performance and resource utilization, reduces latency and provides scalability as needed, for end-user applications in the cloud.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: December 6, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Sanhita Sarkar
  • Patent number: 9477592
    Abstract: A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation. The regions are connected by a plurality of power connectors that convey power from the computing circuit boards to the memory, and a plurality of data connectors that convey data between the first and second regions. The power and data connectors are configured redundantly so that failure of a computing circuit board, a power connector, or a data connector does not interrupt the computation. A method of performing such a computation, and a computer program product implementing the method, are also disclosed.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: October 25, 2016
    Assignee: Silicon Graphics International Corp.
    Inventor: Steven Dean
  • Patent number: 9465712
    Abstract: A method and computer program product for testing a high performance computing application performing a computation within a clustered computer arrangement is disclosed. The high performance computing arrangement performances computations across processors in parallel wherein the processors cooperate to perform the computation. The application can be tested by adding delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the high performance computing arrangement.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: October 11, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Daniel Thomas, John Baron
  • Patent number: 9461422
    Abstract: In an embodiment, a micro ethernet connector includes an outer housing that has a recessed front end and a back end. The micro ethernet connector further includes an inner housing that is disposed within the recessed front end of the outer housing. The inner housing has an exposed end. The exposed end includes a recessed channel. The volume of the recessed channel is substantially equal to the volume of a correspondingly shaped protruding printed circuit board of a male micro ethernet connector. A plurality of spring-biased connectors are disposed within the recessed channel of the inner housing.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 4, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventor: Peter Siltex Yuen
  • Patent number: 9438638
    Abstract: A method at one or more computers having memory and one or more processors includes detecting establishment of a connection between a first process and a second process; determining whether an augmented communications service is available for the connection between the first process and second process; in accordance with a determination that the augmented communications service is available, configuring the connection between the first process and the second process to make use of the augmented communications service with no modification to the executable codes of the first process and the second process; and in accordance with a determination that the augmented communications service is not available, configuring the connection between the first process and the second process to make use of a non-augmented communications service.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 6, 2016
    Assignee: SILICON GRAPHICS INTERNATIONAL CORP.
    Inventors: Michael Andrew Raymond, Andy Warner