Patents Assigned to Silicon Graphics International
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Patent number: 9432299Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: GrantFiled: March 2, 2015Date of Patent: August 30, 2016Assignee: Silicon Graphics International Corp.Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Patent number: 9424098Abstract: Embodiments of the invention relate to a system and method for dynamically scheduling resources using policies to self-optimize resource workloads in a data center. The object of the invention is to allocate resources in the data center dynamically corresponding to a set of policies that are configured by an administrator. Operational parametrics that correlate to the cost of ownership of the data center are monitored and compared to the set of policies configured by the administrator. When the operational parametrics approach or exceed levels that correspond to the set of policies, workloads in the data center are adjusted with the goal of minimizing the cost of ownership of the data center. Such parametrics include yet are not limited to those that relate to resiliency, power balancing, power consumption, power management, error rate, maintenance, and performance.Type: GrantFiled: June 29, 2013Date of Patent: August 23, 2016Assignee: Silicon Graphics International Corp.Inventors: Eng Lim Goh, Christian Tanasescu, George L. Thomas, Charlton Port
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Patent number: 9424091Abstract: A system for deploying big data software in a multi-instance node. The optimal CPU memory and core configuration for a single instance database is determined. After determining an optimal core-memory ratio for a single instance execution, the software is deployed in multi-instance mode on single machine by applying the optimal core-memory ratio for each of the instances. The multi-instance database may then be deployed and data may be loaded in parallel for the instances.Type: GrantFiled: April 30, 2014Date of Patent: August 23, 2016Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: Sanhita Sarkar, Raymon Morcos
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Patent number: 9426932Abstract: A server includes a tray that has a front portion and a back portion. A motherboard is disposed in the front portion of the tray and the motherboard is coupled to a heat sink. A fan is disposed in the back portion of the tray. A hard drive is disposed between the motherboard and the fan and the hard drive is operatively connected to the motherboard. The server also includes a heat pipe that has a body longitudinally bounded by an inlet and an outlet. The inlet is coupled to the heat sink, while the outlet is coupled to the fan. The body of the heat pipe extends past the hard drive. A power supply is also disposed in the tray and is operatively connected to the motherboard, the fan, and the hard drive.Type: GrantFiled: June 29, 2013Date of Patent: August 23, 2016Assignee: Silicon Graphics International Corp.Inventors: Robert Michael Kinstle, Kevin Schlichter, Seitu Barron
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Patent number: 9412412Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.Type: GrantFiled: October 22, 2014Date of Patent: August 9, 2016Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: Kevan Flint Rehm, Judith Ann Schmitz, Joseph Carl Nemeth, John Michael Sygulla
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Patent number: 9405606Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem. At least one trusted metadata server assigns a mandatory access control label as an extended attribute of each filesystem object regardless of whether required by a client node accessing the filesystem object. The mandatory access control label indicates the sensitivity and integrity of the filesystem object and is used by the trusted metadata server(s) to control access to the filesystem object by all client nodes.Type: GrantFiled: September 30, 2013Date of Patent: August 2, 2016Assignee: Silicon Graphics International Corp.Inventor: Kenneth S. Beck
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Patent number: 9389940Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.Type: GrantFiled: February 28, 2013Date of Patent: July 12, 2016Assignee: Silicon Graphics International Corp.Inventors: Mark Larson, Michael Brown, Gary Meyer
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Patent number: 9389760Abstract: A system may provide a visualization function during computational functions performed by a host system. Access to a library of functions including a visualization function is provided. Then, a computing application is executed. The execution of the computing application includes generating multi-dimensional data, invoking the visualization function from the library, and providing a visual representation of at least a portion of the multi-dimensional data for display within the computing application using the visualization function.Type: GrantFiled: June 29, 2013Date of Patent: July 12, 2016Assignee: Silicon Graphics International CorporationInventors: Eng Lim Goh, Hansong Zhang, Chandrasekhar Murthy
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Patent number: 9386100Abstract: A cluster of computing systems is provided with guaranteed real-time access to data storage in a storage area network. Processes issue request for bandwidth reservation which are initially handled by a daemon on the same node as the requesting processes. The local daemon determines whether bandwidth is available and, if so, reserves the bandwidth in common hardware on the local node, then forwards requests for shared resources to a master daemon for the cluster. The master daemon makes similar determinations and reservations for resources shared by the cluster, including data storage elements in the storage area network and grants admission to the requests that don't exceed total available bandwidth.Type: GrantFiled: September 30, 2013Date of Patent: July 5, 2016Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventor: Michael A. Raymond
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Patent number: 9367473Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).Type: GrantFiled: December 26, 2013Date of Patent: June 14, 2016Assignee: Silicon Graphics International Corp.Inventor: Jeffrey S. Kuskin
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Patent number: 9361474Abstract: Resource acquisition requests for a filesystem are executed under user configurable metering. Initially, a system administrator sets a ratio of N:M for executing N read requests for M write requests. As resource acquisition requests are received by a filesystem server, the resource acquisition requests are sorted into queues, e.g., where read and write requests have at least one queue for each type, plus a separate queue for metadata requests as they are executed ahead of any waiting read or write request. The filesystem server controls execution of the filesystem resource acquisition requests to maintain the ratio set by the system administrator.Type: GrantFiled: December 26, 2013Date of Patent: June 7, 2016Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: David Chinner, Michael Anthony Gigante
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Patent number: 9275058Abstract: A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem and operating system implementing DMAPI. Threads executing on a metadata client know when a DMAPI event is required, and generate the DMAPI event on their own initiative when necessary. A metadata server maintains DMAPI queues. If the metadata server relocates to another host, the DMAPI events in the DMAPI queues are moved transparently to users.Type: GrantFiled: August 29, 2011Date of Patent: March 1, 2016Assignee: Silicon Graphics International Corp.Inventors: Geoffrey Wehrman, Dean Roehrich
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Patent number: 9271267Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.Type: GrantFiled: May 22, 2012Date of Patent: February 23, 2016Assignee: Silicon Graphics International Corp.Inventors: Gregory Marlan, Kenneth Yeager, Mahdi Seddighnezhad, David X. Zhang
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Patent number: 9268684Abstract: A high performance computing (HPC) system includes computing blades having a first region that includes processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation and another computing processor for performing data movement and storage. Because data movement and storage are offloaded to the secondary processor, the processors for performing the computation are not interrupted to perform these tasks. A method for use in the HPC system receives instructions in the computing processors and first data in the memory. The method includes receiving second data into the memory while continuing to execute the instructions in the computing processors, without interruption. A computer program product implementing the method is also disclosed.Type: GrantFiled: June 29, 2013Date of Patent: February 23, 2016Assignee: Silicon Graphics International Corp.Inventors: Steven Dean, David R. Collins, Paul Kinyon
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Patent number: 9262799Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.Type: GrantFiled: November 7, 2014Date of Patent: February 16, 2016Assignee: Silicon Graphics International Corp.Inventor: Cheng Liao
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Patent number: 9250826Abstract: A high-performance-computer system includes a statistics accumulation apparatus configured to efficiently accumulate system performance data from a variety of system components, and periodically write such data to processor local memory for efficient subsequent software processing of the thus acquired data, thereby reducing the system hardware and software overhead needed for collection of such data as compared to prior art systems.Type: GrantFiled: March 13, 2013Date of Patent: February 2, 2016Assignee: Silicon Graphics International Corp.Inventor: Eric Carl Fromm
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Patent number: 9252812Abstract: A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.Type: GrantFiled: March 28, 2014Date of Patent: February 2, 2016Assignee: Silicon Graphics International Corp.Inventors: Mark Ronald Sikkink, John Francis De Ryckere
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Patent number: 9240940Abstract: In accordance with some implementations, a method for evaluating large scale computer systems based on performance is disclosed. A large scale, distributed memory computer system receives topology data, wherein the topology data describes the connections between the plurality of switches and lists the nodes associated with each switch. Based on the received topology data, the system performs a data transfer test for each of the pair of switches. The test includes transferring data between a plurality of nodes and determining a respective overall test result value reflecting overall performance of a respective pair of switches for a plurality of component tests. The system determines that the pair of switches meets minimum performance standards by comparing the overall test result value against an acceptable test value. If the overall test result value does not meet the minimum performance standards, the system reports the respective pair of switches as underperforming.Type: GrantFiled: March 15, 2013Date of Patent: January 19, 2016Assignee: Silicon Graphics International Corp.Inventor: John Baron
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Patent number: 9237093Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.Type: GrantFiled: March 14, 2013Date of Patent: January 12, 2016Assignee: Silicon Graphics International Corp.Inventors: Joseph George Tietz, Gregory Michael Thorson, Eric C. Fromm
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Patent number: 9229497Abstract: A high performance computing system includes one or more blade enclosures having a cooling manifold and configured to hold a plurality of computing blades, and a plurality of computing blades in each blade enclosure with at least one computing blade including two computing boards. The system further includes two or more cooling plates with each cooling plate between two corresponding computing boards within the computing blade, and a fluid connection coupled to the cooling plate(s) and in fluid communication with the fluid cooling manifold.Type: GrantFiled: June 28, 2013Date of Patent: January 5, 2016Assignee: Silicon Graphics International Corp.Inventors: Steven J. Dean, Richard B. Salmonson, Russell E. Stacy, Roger Ramseier, Mark Maloney