Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.

Abstract: Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.

Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.

Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.

Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract: A memory system having a memory controller, interface device and plurality of memory elements. The interface device is coupled to the memory controller via a first high-speed signal path. The plurality of memory elements are removably coupled to the interface device via respective second signal paths, each of the second signal paths having a lower signaling bandwidth than the first signaling path.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.

Abstract: A multilayered circuit component includes one or more substrates. A first surface of one of the substrates includes circuit paths and other current carrying elements. A second surface of the same or another substrate also includes circuit paths and other current carrying elements. An aperture extends through at least a portion of the one or more substrates. The aperture is defined by a first opening on the first surface, a second opening on the second surface, and an internal surface of the one or more substrates that extends between the first surface and the second surface. A first trace element is provided over a portion of the internal surface of the aperture to extend between the first surface and the second surface. The first trace element extends onto the first surface to form a first partial perimeter of the first opening. A second trace element is provided over a portion of the internal surface of the aperture to extend between the first surface and the second surface.

Abstract: The dielectric constant and loss tangent of a transmission structure is lowered by sandwiching a conductor between two dielectric structures one or both of which have a series of openings. The conductor is formed so that the conductor is formed across each opening of each dielectric structure. The dielectric structures provide structural support while exposing a significant portion of the conductor to air, thereby forming a transmission structure with an largely air-dielectric.