Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous SixC1-x wherein 0<x<1, and wherein the SixC1-x incorporates at least one impurity selected from the group consisting of hydrogen, halogens, nitrogen, oxygen, sulphur, selenium, transition metals, boron, aluminum, phosphorus, gallium, arsenic, lithium, beryllium, sodium and magnesium.

Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous Si.sub.x C.sub.1-x wherein 0<x<1, and wherein the Si.sub.x C.sub.1-x incorporates at least one impurity selected from the group consisting of hydrogen, halogens, nitrogen, oxygen, sulphur, selenium, transition metals, boron, aluminum, phosphorus, gallium, arsenic, lithium, beryllium, sodium and magnesium.

Abstract: An electron emitter suitable for a flat-panel CRT display is fabricated by a process in which charged particles are passed through a track layer (144) to create charged-particle tracks (146.sub.1). The track layer is etched along the tracks to form apertures (148.sub.1) that are employed in defining corresponding cap regions (150A) over an underlying emitter layer (142). After removing the track layer, part of the emitter layer is removed using the cap regions as masks to control the extent of the emitter material removed. Electron-emissive elements (142D), typically in the shape of cones, are thereby formed in the remainder (142C) of the emitter layer. The electron emitter can also be provided with a gate electrode (158C).

Abstract: A face plate for a cathode ray tube display is produced by a method in which small holes are formed through a sheet of unfired ceramic tape. The holes are arranged in a desired pattern for the location of pixel dots. The holes are filled with generally transparent glass to form plugs in the desired pattern. The ceramic tape is cured to a hardened state by firing to an appropriate temperature. Each plug is coated at an inner, anode side of the face plate with phosphor of appropriate color.

Abstract: A flat panel device contains a faceplate, a backplate, a light-emitting mechanism, and a spacer. The faceplate is connected to the backplate to form a sealed enclosure. The spacer is situated within the enclosure and supports the two plates against forces acting towards the enclosure. The spacer can take various forms and can be constituted with various materials. In one embodiment, the spacer includes a spacer wall formed with multiple sheets of laminated material consisting of ceramic, glass-ceramic, ceramic reinforced glass, devitrifying glass, or metal coated with electrical insulation. In another embodiment, the spacer includes a spacer wall having a surface that follows a non-straight path adjacent the faceplate. In yet another embodiment, the spacer is a spacer structure through which a plurality of holes extends. The light-emitting mechanism is typically implemented with an electron-emitting cathode and light-emissive material situated over the faceplate.

Abstract: A method is provided for creating gated filament structures for a field emission display. A multi-layer structure is provided that includes a substrate, an insulating layer, a metal gate layer positioned on a top surface of the insulating layer and a gate encapsulation layer positioned on a top surface of the metal gate layer. A plurality of gates are provided and define a plurality of apertures on the top of the insulating layer. A plurality of spacers are formed in the apertures at their edges on the top surface of the insulating layer. The spacers are used as masks for etching the insulating layer and form a plurality of pores in the insulating layer. The pores are plated with a filament material to create a plurality of filaments. The pores can be overplated to create the plurality of filaments. The filaments are vertically self-aligned in the pores.

Abstract: A field emission display device has a faceplate and a backplate. The faceplate includes a faceplate interior side with an active region made of a plurality of phosphor pixel elements; and the backplate has a backplate interior side with a plurality of field emitters. Sidewalls are positioned between the faceplate and the backplate, to form an enclosed sealed envelope between the sidewalls, backplate interior side and the faceplate interior side. At least one spacer wall in the envelope supports the backplate and the faceplate against forces acting in a direction toward the envelope. At least one internal structure fixes and constrains the faceplate and the backplate, and aligns a plurality of phosphor pixels with corresponding field emitters. Additionally, the faceplate can include at least one faceplate fiducial, and the backplate include a corresponding backplate fiducial. The faceplate fiducial is optically aligned with the backplate fiducial. First, the spacer wall is positioned in the wall gripper.

Abstract: An optical device contains first and second plates (302 and 303), a pattern of ridges (314) situated over the first plate, light-emissive regions (313) situated in spaces between the ridges, electron-emissive elements (309) situated over the second plate, and supporting structure (308) that maintains a desired spacing between the plates. The electron-emissive elements emit electrons that strike the light-emissive regions, causing them to produce light of various colors. The ridges, which extend further away from the first plate than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region formed with metal, ceramic, semiconductor, or/and carbide. The ridges thereby form a raised black matrix that improves contrast and color purity.

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract: A gated area field emitter is fabricated according to a process in which charged-particle tracks are utilized in creating small electron-emissive elements self-aligned to corresponding gate openings in the gate electrode. The electron-emissive elements can have various shapes, including (a) a pedestal, typically a filament, having a pointed tip, (b) a cone, and (c) a combination of a pedestal and an overlying cone whose base diameter is greater than the pedestal's diameter. Each electron-emissive element can be formed as a highly resistive portion and an overlying electron-emissive portion.

Abstract: A gated electron-emitting device contains a multiplicity of electron-emissive elements, each formed with a pedestal (98) and an overlying cone (94.sub.1). In each electron-emissive element, the base diameter of the cone is greater than the element, the base diameter of the cone is greater than the diameter of the pedestal. With the pedestal being electrically conductive, the cone may be electrically resistive. Alternatively, each electron-emissive element can be an elongated element (30B) that reaches a maximum diameter at a point between, and spaced apart from, both ends of the element.

Abstract: An electron emitter contains a gate layer (38), an underlying dielectric layer (36), an intermediate non-insulating layer (34) situated below the dielectric layer, and a lower non-insulating region (32) situated below the intermediate non-insulating layer. A multiplicity of electron-emissive particles (42) are situated over the non-insulating region at the bottom of an opening (40) extending through the three layers. The ratio of the thickness of the dielectric layer to the thickness of the intermediate non-insulating layer is in the range of 1:1 to 4:1, while the ratio of the mean diameter of the opening to the thickness of the intermediate non-insulating layer is in the range 1:1 to 10:1. The presence of the intermediate non-insulating layer improves the collimation of the beam of electrons emitted from the electron-emissive elements. The electron emitter is manufactured according to a simple, readily controllable process.

Abstract: A faceplate for a field emission display includes a substrate defining a faceplate interior side. Pluralities of phosphor pixels are disposed on the faceplate interior side. A black matrix grid is formed of column and row guard bands on the faceplate interior side. At least one wall gripper is formed in a column or row guard band, with the wall gripper adapted to receive a spacer wall and mount it relative to the pluralities of phosphor pixels. The faceplate can include a faceplate fiducial that optically aligns to a corresponding backplate fiducial. A spacer wall is positioned in the wall gripper and mounted relative to a corresponding locator formed on a backplate interior side. The wall gripper includes a receiving trench that is positioned adjacent to a plurality of deformation accommodation gaps.

Abstract: A grid which controls electron flow, placed between a field emitter cathode and fluorescent anode in a flat cathode ray tube improves focusing, and reduces the switching voltage necessary to stop electron flow. The focusing capabilities of the grid enable increased distance between the cathode and anode, permitting higher anode voltage and use of more efficient phosphors. With the grid, electron flow on/off addressing can be done with drivers operating at less than 30 V, thereby reducing capacitive power loss over prior art addressable arrays and permitting use of inexpensive CMOS control circuitry. The grid's switching capabilities enable the use of a simplified field emitter cathode structure with resistive gate films which increase emitter reliability, emitter life, and, for cathode ray tube displays, the uniformity of the display.

Abstract: A flat panel display includes a faceplate and an opposing backplate. The two are sealed together and a sealed envelope is created that includes an active area of length L.sub.1. The active layer includes addressable pixels on the faceplate. Spacers are perpendicular to the faceplate and backplate. The length of a spacer is in a direction parallel to the plane of the faceplate. At least one spacer is positioned in the envelope and provides rigidity to the display. This is required because of the high vacuum which is maintained within the envelope. One or more electrodes are formed on an exterior surface of the spacer. The electrodes extend a length of L.sub.2 along a side of the spacer that is at least equal to L.sub.1. Voltages applied to the electrodes are controlled to achieve a desired voltage distribution between the backplate and the faceplate. The electrode is made of a material with a sheet resistance of less than about 10.sup.5 to 10.sup.7 .OMEGA./.quadrature..

Abstract: A gated field-emission structure contains a emitter electrode (46), an overlying electrically insulating layer (48, and one or more electron-emissive elements (52) situated in one or more apertures extending through the insulating layer. A patterned gate electrode (50) through which each electron-emissive element is exposed overlies the insulating layer. Focusing ridges (54) are situated on the insulating layer on opposite sides of the gate electrode. The focusing ridges, which normally extend to a considerably greater height than the gate electrode, cause emitted electrons to converge into a narrow band.

Abstract: A light-emitting structure (306) contains a main section (302), a pattern of ridges (314) situated along the main section, and a plurality of light-emissive regions (313) situated in spaces between the ridges. The light-emissive regions produce light of various colors upon being hit by electrons. The ridges, which extend further away from the main section than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region. The ridges thereby form a raised black matrix that improves contrast and color purity. The dark region of each ridge may be formed with metal, ceramic, semiconductor, or carbide. Each ridge may include an additional region (314b) of different chemical composition than the dark region.

Abstract: A field-emission structure suitable for large-area flat-panel televisions centers around an insulating porous layer (24A) that overlies a lower conductive region (22) situated over insulating material of a supporting substrate (20). Electron-emissive filaments (30) occupy pores (28) extending through the porous layer. A conductive gate layer (34A) through which openings (36) extend at locations centered on the filaments typically overlies the porous layer. Cavities (38) are usually provided in the porous layer along its upper surface at locations likewise centered on the filaments.In fabricating the structure, the pores are preferably formed by etching charged-particle tracks. Electrochemical deposition is employed to selectively create the filaments in the pores. Self-alignment of the gate openings to the filaments is achieved with charged-particle track etching and/or further electrochemical processing.

Abstract: A flat screen cathode ray tube is self supporting of a phosphor coated glass face place in that a multiplicity of support points or lines of support extend from an addressing grid structure to contact the inside surface of the face plate between pixels. A cathode or back plate is similarly supported against the addressing structure. The addressing structure itself is formed of a series of ceramic plates or layers, assembled in an unfired state wherein the ceramic and/or glass materials are held together with a plastic binder and are flexible and easily handled. A matrix of very small holes is formed in each plate, one hole for each of the R, G and B components of each pixel in a color display.