Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230014476
    Abstract: An electronic package, in which a heat dissipation structure is disposed on a carrier structure to form a packaging space for electronic components to be accommodated in the packaging space, and the electronic components are completely encapsulated by a heat dissipation material to prevent the electronic components exposing from the heat dissipation material so as to improve the heat dissipation effect.
    Type: Application
    Filed: June 27, 2022
    Publication date: January 19, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Method for fabricating electronic package and carrier structure thereof
    Patent number: 11545385
    Abstract: A carrier structure having a strengthening layer is provided. The strengthening layer comprises 5 to 30% by weight polysiloxane, 1 to 20% by weight silicon dioxide, and 60 to 85% by weight polyethylene terephthalate (PET) film. The carrier structure is used in a semiconductor packaging process for improving the process reliability.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 3, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Tse-Yuan Lin, Chun-Ming Laio, Yu-Chih Cheng
  • FLIP-CHIP PROCESS AND BONDING EQUIPMENT
    Publication number: 20220406642
    Abstract: A flip-chip process is to provide a pressing jig with a channel, so that the pressing jig grips a chip module by vacuum suction through the channel, and the chip module can be bonded onto a circuit board via a plurality of solder bumps through the pressing jig, and then a heating device is provided to heat the plurality of solder bumps and reflow the plurality of solder bumps. Therefore, the chip module can be vacuum-gripped by the pressing jig to suppress deformation of the chip module, so that the solder bumps can effectively connect to corresponding contacts of the circuit board.
    Type: Application
    Filed: August 3, 2021
    Publication date: December 22, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Electronic package
    Patent number: 11532568
    Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Yu-Wei Yeh, Tsung-Hsien Tsai, Chi-Liang Shih, Sheng-Ming Yang, Ping-Hung Liao
  • Electronic package and manufacturing method thereof
    Patent number: 11532528
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Testing device for burn-in test operations and control method thereof
    Patent number: 11531059
    Abstract: A control method is provided and used to place a target object on a test platform in a cabin of a testing device, to sense the temperature of the target object by a temperature response structure, and then to receive temperature signals of the temperature response structure by a controller, where the controller can regulate the pressure inside the cabin to control the air pressure of the cabin, so that the target object can still maintain good heat dissipation under high power consumption.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Ming Tu, Chih-Ming Yang, Wen-Chin Liang, Cheng-Shao Chen, Yung-Ming Wang
  • Chip matching system and method thereof
    Patent number: 11532495
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220399246
    Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 15, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Yu-Po Wang
  • ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220399245
    Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.
    Type: Application
    Filed: July 8, 2021
    Publication date: December 15, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Method for fabricating substrate structure
    Patent number: 11527491
    Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 13, 2022
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Po-Hao Wang, Chun-Tang Lin, Shou-Qi Chang, Yu-Hsiang Hsieh
  • Electronic package, supporting structure and fabrication method thereof
    Patent number: 11527472
    Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: December 13, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cho-Hsin Chang, Hao-Ju Fang, Ting-Wei Chi, Te-Fang Chu
  • TESTING EQUIPMENT
    Publication number: 20220390509
    Abstract: A testing equipment is provided, in which at least one testing module is disposed on a machine, and the testing module includes a circuit board, a testing carrier disposed on the circuit board and carrying a target object, and a processor disposed on the circuit board and electrically connected to the testing carrier, such that the testing module can operate and process a target information of the target object by itself via the processor, without connecting to an external computer to operate and process the target information of the target object, so as to quickly obtain a detecting information of the target object.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 8, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Li-Wei Lee, Yung-Ming Wang, Ping-Chieh Huang, Tien-Yao Hsu
  • Electronic package and manufacturing method thereof
    Patent number: 11521930
    Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: December 6, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Testing device and method
    Patent number: 11513152
    Abstract: Provided is a testing method including: disposing a wafer on a working platform of a testing device; and moving a circuit board of the testing device relative to the working platform by a movement assembly of the testing device so as to allow at least two testing ports of the circuit board to test two chips of the wafer, respectively. Further, the two testing ports have different testing functions. Therefore, during the wafer testing process, a single testing device can perform multiple testing operations.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: November 29, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wen-Chin Liang, Po-Wen Hsiao, Cheng-Tsai Hsieh, Cheng-Shao Chen
  • Package stack structure and method for manufacturing the same
    Patent number: 11516925
    Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Han-Hung Chen, Yuan-Hung Hsu, Chang-Fu Lin, Rung-Jeng Lin, Fu-Tang Huang
  • ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220375822
    Abstract: An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 24, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Siang-Yu Lin, Wen-Jung Tsai, Chia-Yang Chen, Chien-Cheng Lin
  • ELECTRONIC PACKAGE, HEAT DISSIPATION STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220375813
    Abstract: A heat dissipation structure is provided and includes a heat dissipation body and an adjustment channel. A carrying area and an active area adjacent to the carrying area are defined on a surface of the heat dissipation body, the carrying area is used for applying a first heat dissipation material thereonto, and the adjustment channel is formed in the active area, where one end of the adjustment channel communicates with the outside of the heat dissipation structure, and the other end communicates with the carrying area. Therefore, when the heat dissipation body is coupled to the electronic component by the first heat dissipation material, the adjustment channel can adjust a volume of the first heat dissipation material.
    Type: Application
    Filed: January 25, 2022
    Publication date: November 24, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Kuo-Hua Yu, Chang-Fu Lin
  • ELECTRONIC PACKAGE AND ANTENNA STRUCTURE THEREOF
    Publication number: 20220359975
    Abstract: An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Chu Lai, Ho-Chuan Lin, Min-Han Chuang
  • ELECTRONIC MODULE, MANUFACTURING METHOD THEREOF AND ELECTRONIC PACKAGE HAVING THE SAME
    Publication number: 20220359374
    Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang
  • ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220359324
    Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai